PI90LV386/PI90LVT386
High-Speed Differential Line Receivers
Description
Features
• Sixteen line receivers meet or exceed the requirements of the
ThePI90LVx386familyconsistsof sixteendifferentiallinereceivers
with 3-state outputs that implement Low-Voltage Differential
Signaling (LVDS). Any of the differential receivers will provide a
valid logical output state with a ±100mV differential input voltage
withintheinputcommon-modevoltagerangethatallows0to3Vof
groundpotentialdifferencebetweentwoLVDSnodes.Theindepen-
dentENpinscanbeusedtoplacetheoutputsineitheranormallogic
state (high or low logic levels) or a high-impedance state. In high-
impedance state, outputs neither load nor drive the bus lines.
The intended application of these devices, and their signaling
techniques, is for point-to-point baseband data transmission over
controlled impedance media of approximately 100-ohms with a
100-Ohmterminationresistor.ThePI90LVT386integratesthetermi-
nating resistors while the PI90LV386 requires external resistors.
The transmission media may be printed circuit board traces,
backplanes,orcables.ThePI90LV386’s16receiversintegratedinto
the same substrate allow precise timing alignment.
ANSITIA/EIA-644-1995Standard
• Designed for signaling rates up to 660 Mbps
• 0V to 3V common-mode input voltage range
• Operates from a single 3.3V supply
• Typical propagation delay time: 2.6ns
• Output skew 100ps (typical)
• Part-to-part skew is less than 1ns
• Integrated110-OhmterminationonPI90LVT386
• LowVoltageTTL(LVTTL)levelsare5Vtolerant
• Open-circuitfailsafe
• Flow-through pin out
• Packaging(Pb-free&Greenavailable):
-64-PinThinShrinkSmallOutputTSSOP(A)
PinConfiguration
These parts are characterized for operation from –40°C to 85°C.
1R
1R
1R
1R
1R
1R
1R
1R
2R
2R
2R
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
IN1+
IN1–
IN2+
IN2–
IN3+
IN3–
IN4+
IN4–
IN1+
IN1–
IN2–
V
2
CC
V
3
CC
BlockDiagram
4
GND
EN1
1R
5
6
OUT1
1R
1R
1R
7
OUT2
OUT3
OUT4
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EN2
2R
OUT1
2R
2R
2R
2R
2R
OUT2
OUT3
OUT4
IN2–
IN3+
2R
2R
2R
IN3–
IN4+
IN4–
64-Pin
A
GND
V
CC
V
3R
3R
CC
IN1+
GND
3R
IN1–
3R
3R
3R
3R
3R
OUT1
IN2+
IN2–
IN3+
IN3–
IN4+
3R
3R
3R
OUT2
OUT3
OUT4
EN3
4R
3R
4R
4R
OUT1
IN4–
IN1+
IN1–
4R
4R
4R
OUT2
OUT3
OUT4
4R
4R
4R
4R
4R
4R
IN2+
IN2–
IN3+
IN3–
IN4+
IN4–
EN4
GND
V
CC
V
CC
GND
16 Receivers
PS8574B
10/04/04
1