PI90LV211QE

更新时间： 2024-11-15 22:44:27

品牌	Logo	应用领域
百利通 - PERICOM		时钟
页数	文件大小	规格书
9页	186K
描述
1:6 Differential Clock Distribution Chip

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数据手册

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PI90LV211QE 数据手册

PI90LV211/PI90LVT211

1:6 Differential Clock Distribution Chip

Description

Features

ThePI90LV211implementslowvoltagedifferentialsignaling(LVDS)

to achieve clocking rates as high as 320 MHz with low skew. The

PI90LV211isalowskew1:6fanoutdevicedesignedexplicitlyforlow

skew clock distribution applications. The device features a multi-

plexedclockinputtoallowforthedistributionofalowerspeedscan

ortestclockwiththehigh-speedsystemclock.WhenLOW theSEL

pin will select the differential clock input.

Both a common enable and individual output enables are provided.

WhenassertedthepositiveoutputwillgoLOWonthenextnegative

transition of the CLK (or SCLK) input. The enable function is

synchronoussothattheoutputswillonlybeenabled/disabledwhen

they are already in the LOW state. This avoids any chance of

generating a runt clock pulse when the device is enabled/disabled

as can happen with an asynchronous control. The internal flip flop

is clocked on the falling edge of the input clock, therefore all

associated specification limits are referenced to the negative edge

of the clock input.

• MeetsorExceedsRequirementsofANSITIA/EIA-644-1995

• Designed for Clocking Rates up to 320MHz

• Operates from a single 3.3-V Supply

• Low-VoltageDifferentialSignaling(LVDS)withOutput

Voltagesof±350mVintoa100-ohmload

• Choice between LVDS or TTL clock input

• Synchronous Enable/Disable

• Multiplexedclockinput

– Internal 300 kohm pullup resistor on all control pins

–CLKandCLKhave110-ohmtermination(PI90LVT211)

• Common and individual Enable/Disable control

• 50ps Output-to-Output Skew

• ±24psPeriodJitter

• Bus Pins are High Impedance when disabled or with V <1.5V

• TTL Inputs are 5V Tolerant

• Power Dissipation at 300 MHz

• P190LV211 isfunctionallycompatiblewithMotorola’s

(PECL)MC10E211/MC100E211

• >12kVESDProtection

Individual synchronous enable controls and multiplexed clock in-

puts make this device ideal as the first level distribution unit in a

distributiontree. Theindividualenablescouldbeusedtoallowforthe

disabling of individual cards on a backplane in fault tolerant designs.

• Packaging(Pb-free&Greenavailable):

-28-pinTSSOP(L)

-28-pin QSOP(Q)

FunctionTable

BlockDiagram&PinConfiguration

CLK/CLK SCLK SEL ENx CEN CLK OUT (±)

H/L

↓

CLK

SCLK

V_CC

EN1

V_CC

↓

CLK1_OUT+

↓

Z**

CLK1_OUT–

GND

EN2

ENx disables individual banks

CLK2_OUT+

CLK2_OUT–

SCLK

CLK

** CEN disables all six banks

↓ = NegativetransitionofCLKorSCLK

Z = High Impedance

PI90LVT211

Only

110Ω

CLK3_OUT+

CLK3_OUT–

CLK

EN3

CLK4_OUT+

CLK4_OUT–

SEL

EN4

CLK5_OUT+

CLK5_OUT–

EN5

EN6

CLK6_OUT+

CLK6_OUT–

CEN

GND

PS8535C

10/04/04

12 3 4 5 6 7...9

中文翻译

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与PI90LV211QE相关器件

型号	品牌	获取价格	描述	数据表
PI90LV211QEX	PERICOM	获取价格	Low Skew Clock Driver, 90LV Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 0.150
PI90LV211QX	PERICOM	获取价格	Low Skew Clock Driver, 90LV Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 0.150
PI90LV3486	PERICOM	获取价格	LVDS High-Speed Differential Line Receivers
PI90LV3486L	PERICOM	获取价格	LVDS High-Speed Differential Line Receivers
PI90LV3486LE	PERICOM	获取价格	LVDS High-Speed Differential Line Receivers
PI90LV3486W	PERICOM	获取价格	LVDS High-Speed Differential Line Receivers
PI90LV3486WE	PERICOM	获取价格	LVDS High-Speed Differential Line Receivers
PI90LV3487	ETC	获取价格	LVDS \| Quad LVDS Driver (Dual EN)
PI90LV3487LE	PERICOM	获取价格	Line Driver, 4 Func, 4 Driver, PDSO16, GREEN, TSSOP-16
PI90LV3487WE	PERICOM	获取价格	Line Driver, 4 Func, 4 Driver, PDSO16, 0.150 INCH, GREEN, SOIC-16

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