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PI74AVC16821AX PDF预览

PI74AVC16821AX

更新时间: 2024-11-06 10:33:51
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管
页数 文件大小 规格书
5页 311K
描述
Bus Driver, AVC Series, 2-Func, 10-Bit, True Output, CMOS, PDSO48, 0.240 INCH, PLASTIC, TSSOP-48

PI74AVC16821AX 数据手册

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ADVANCE INFORMATION  
PI74AVC16821  
PI74AVCH16821  
20-Bit Bus Interface Flip-Flop  
with 3-State Outputs  
Product Features  
Description  
Pericom Semiconductor’s PI74AVC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
Designed for low voltage operation, VCC = 1.65V to 3.6V  
Sub 2.0ns delays at 2.5V and 3.3V  
Dynamic Impedance Control on outputs, current  
drive > ±24mA at 2.5VCC  
This 20-bit bus interface flip-flop can be used as two 10-bit flip-  
flops or one 20-bit flip-flops. The 20 flip-flops are edge-triggered  
D-type flip-flops. On the positive transition of the clock (CLK)  
input, the device provides true data at the Q outputs.  
Patented noise reduction circuit  
I/O Tolerant to 3.6V, Inputs and Outputs for  
mixed voltage systems  
A buffered output-enable (OE) input can be used to place the ten  
outputsineitheranormallogicstate(HIGHorLOWlevel)orahigh-  
impedance state. In the high-impedance state, the outputs neither  
loadnordrivethebuslinessignificantly.Thehigh-impedancestate  
and increased drive provide the capacity to drive bus lines without  
the need for interface or pullup components.  
Supports live insertion  
Industrial operation at -40°C to +85°C  
Available Packages:  
– 48-pin 240 mil wide plastic TSSOP (A48)  
– 48-pin 173 mil wide plastic TVSOP (K48)  
OE does not affect the internal operation of the flip-flops. Old data  
can be retained or new data can be entered while the outputs are in  
the high-impedance state.  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pullup resistor; the  
minimum value of the resistor is determined by the current sinking  
capability of the driver.  
ThePI74AVCH16821has“BusHold”whichretainsthe data input’s  
laststatewheneverthedatainputgoestohighimpedancepreventing  
“floating”inputsandeliminatingtheneedforpullup/downresistors.  
LogicBlockDiagram  
1
28  
1OE  
2OE  
56  
55  
29  
42  
1CLK  
2CLK  
One of Ten  
Channels  
One of Ten  
Channels  
C
1
C1  
2
15  
1D  
1
1Q  
1
2D  
1
2Q1  
1
D
1D  
TO 9 OTHER CHANNELS  
TO 9 OTHER CHANNELS  
PSXXXX  
02/01/99  
1

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