PI74ALVCH16374VX

更新时间： 2024-09-16 12:58:35

品牌	Logo	应用领域
百利通 - PERICOM		触发器
页数	文件大小	规格书
5页	338K
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PI74ALVCH16374VX 数据手册

PI74ALVCH16374

16-Bit Edge Triggered D-Type Flip-Flop

with 3-State Outputs

Product Features

Product Description

Pericom Semiconductors PI74ALVCH series of logic circuits are

producedintheCompanysadvanced0.5micronCMOStechnology,

achieving industry leading speed.

• PI74ALVCH16374 is designed for low voltage operation

• V = 2.3V to 3.6V

• Hysteresis on all inputs

This 16-bit edge-triggered D-type flip-flop is designed for 2.3V to

• Typical V

(Output Ground Bounce)

OLP

3.6V V operation.

< 0.8V at V = 3.3V, T = 25°C

The PI74ALVCH16374 is particularly suitable for implementing

buffer registers, I/O ports, bidirectional bus drivers, and working

registers. This device can be used as two 8-bit flip-flops or one

16-bit flip-flop. On the positive transition of the Clock (CLK)

input, the Q outputs of the flip-flop take on the logic levels set up

at the data (D) inputs. OE can be used to place the eight outputs in

either a normal logic state (high or low logic levels) or a high-

impedance state. In that state, the outputs neither load nor drive the

buslinessignificantly. Thehigh-impedancestateandtheincreased

drive provide the capability to drive bus lines without need for

interface or pullup components. OE does not affect internal

operations of the flip-flop. Old data can be retained or new data can

be entered while the outputs are in the high-impedance state.

• Typical V

(Output V Undershoot)

OHV

< 2.0V at V = 3.3V, T = 25°C

• Bus Hold retains last active bus state during 3-STATE

eliminating the need for external pullup resistors

• Industrial operation at 40°C to +85°C

• Packages available:

48-pin 240 mil wide plastic TSSOP (A)

48-pin 300 mil wide plastic SSOP (V)

Logic Block Diagram

To ensure the high-impedance state during power up or power

1OE

down, OE should be tied to V through a pullup resistor; the

minimum value of the resistor is determined by the current-sinking

capability of the driver.

1CLK

Active bus-hold circuitry is provided to hold unused or floating

data inputs at a valid logic level.

1Q1

1D1

To Seven Other Channels

2OE

2CLK

2Q1

2D1

To Seven Other Channels

PS8138A 09/03/98

12 3 4 5

中文翻译

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与PI74ALVCH16374VX相关器件

型号	品牌	获取价格	描述	数据表
PI74ALVCH16500	ETC	获取价格	Logic \| 18-Bit Universal Bus Transceiver
PI74ALVCH16500A	PERICOM	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
PI74ALVCH16500AEX	PERICOM	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
PI74ALVCH16500AX	PERICOM	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
PI74ALVCH16500V	ETC	获取价格	18-Bit Bus Transceiver
PI74ALVCH16500VE	PERICOM	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
PI74ALVCH16500VX	PERICOM	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
PI74ALVCH16501	PERICOM	获取价格	18-Bit Universal Bus Transceiver With 3-State Outputs
PI74ALVCH16501A	ETC	获取价格	18-Bit Bus Transceiver
PI74ALVCH16501AEX	PERICOM	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO48,

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