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PI3EQX1004B1ZHEX

更新时间： 2024-11-21 21:19:55
品牌 Logo 应用领域
美台 - DIODES 电信电信集成电路
页数 文件大小 规格书
11页 1443K
描述
Telecom Circuit,

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中文翻译

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PI3EQX1004B1ZHEX 技术参数

生命周期：Active包装说明：TQFN-42
Reach Compliance Code：unknownFactory Lead Time：34 weeks
风险等级：1.48JESD-30 代码：R-XQCC-N42
长度：9 mm功能数量：1
端子数量：42最高工作温度：70 °C
最低工作温度：封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：RECTANGULAR
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度：0.84 mm
标称供电电压：3.3 V表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT温度等级：COMMERCIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：3.5 mm
Base Number Matches：1

PI3EQX1004B1ZHEX 数据手册

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A product Line of  
Diodes Incorporated  
PI3EQX1004B1  
2-Port USB3.1 Gen-2 10Gbps ReDriver  
Features  
Description  
ꢀÎ5 & 10Gbps serial link with linear equalizer  
ꢀÎUSB3.1 and USB3.0 Compatible  
ꢀÎFull Compliancy to USB3.1 Super Speed Standard  
ꢀÎFour 10Gbps differential signal pairs  
ꢀÎPin Adjustable Receiver Equalization  
ꢀÎPin Adjustable Flat Gain  
ꢀÎ100Ω Differential CML I/O’s  
ꢀÎAutomatic Receiver Detect  
ꢀÎAuto "Slumber" mode for adaptive power management  
ꢀÎSingle Supply Voltage: 3.3V  
ꢀÎPackaging:  
e PI3EQX1004B1 is a low power, high performance 10.0 Gbps  
2-Port USB 3.1 linear ReDriver™ designed specifically for the USB  
3.1 protocol.  
e device provides programmable equalization, and flat gain to  
optimize performance over a variety of physical mediums by re-  
ducing Inter-Symbol Interference. PI3EQX1004B1 supports two  
100Ω Differential CML data I/O’s between the Protocol ASIC to  
a switch fabric, over cable, or to extend the signals across other  
distant data pathways on the user’s platform.  
e integrated equalization circuitry provides flexibility with  
signal integrity of the signal before the ReDriver. Each channel  
operates fully independently. e channels’ input signal level de-  
termines whether the output is active.  
Î42-pin, TQFN 3.5 x 9mm (ZH42)  
e PI3EQX1004B1 also includes an automatic receiver detect  
function. e receiver detection loop will be active again if the  
corresponding channel’s signal detector is idle for longer than  
7.3ms. e channel will then move to Unplug Mode if load not  
detected, or it will return to Low Power Mode (Slumber Mode)  
due to inactivity.  
Block Diagram  
Input Level detect  
to control logic  
+
–
+
–
RXAP  
TXAP  
+
–
+
TXAN  
–
RXAN  
Equalizer  
EQA  
Output buꢀer  
Flat gain FGA  
Equalizer  
EQB  
Flat gain FGB  
Output buꢀer  
TXBP  
RXBP  
+
–
+
–
+
–
Figure1  
RXBN  
TXBN  
+
–
Input Level detect  
to control logic  
Pericom  
Input Level detect  
to control logic  
PC Monitor  
+
–
USB 3.1  
Pericom  
ReDriver  
USB 3.1  
ReDriver  
+
–
RXCP  
TXCP  
+
–
+
TXCN  
–
RXCN  
Equalizer  
EQC  
Output buꢀer  
Flat gain FGC  
Notebook  
Smart Phone  
Equalizer  
EQD  
Flat gain FGD  
Output buꢀer  
TXDP  
RXDP  
+
–
+
–
+
–
RXDN  
TXDN  
+
–
Input Level detect  
to control logic  
EQA/B/C/D  
FGA/B/C/D  
FG/EQ  
Control Logic  
External Storage  
USB 3.0 Cable  
Device  
EN_AB/EN_CD  
Power Management  
www.diodes.com  
September 2017  
Diodes Incorporated  
PI3EQX1004B1  
Document Number DS40596 Rev 2-2  
1
1234567...11

中文翻译

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