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PI3EQX4951BZDE PDF预览

PI3EQX4951BZDE

更新时间: 2024-11-25 15:47:51
品牌 Logo 应用领域
百利通 - PERICOM 接口集成电路
页数 文件大小 规格书
9页 741K
描述
Interface Circuit, 4 X 4 MM, GREEN, MO-220, TQFN-20

PI3EQX4951BZDE 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFN
包装说明:4 X 4 MM, GREEN, MO-220, TQFN-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:N接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:S-XQCC-N20JESD-609代码:e3
长度:4 mm功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:0.8 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:4 mmBase Number Matches:1

PI3EQX4951BZDE 数据手册

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PI3EQX4951B  
3.3V, 1-port, SATA2 i/m ReDriver™ with Analog/Digital Configuration  
Features  
Description  
ÎSATA2 i, m; external SATA2  
Pericom Semiconductor’s PI3EQX4951B is a low power, signal  
ReDriver™. The device provides programmable equalization,  
to optimize performance over a variety of physical mediums  
by reducing Inter-Symbol Interference. PI3EQX4951B supports  
two 100Ω Differential CML data I/O’s between the Protocol  
ASIC to a switch fabric, across a backplane, or to extend the  
signals across other distant data pathways on the user’s plat-  
form.  
ÎTwo 3.0Gbps differential signal pairs  
ÎIndependent Digital Output Emphasis Control  
Î100Ω Differential CML I/O’s  
ÎInput signal level detect and squelch for each channel  
ÎOOB Support  
ÎEnhanced Mode Features:  
The integrated equalization circuitry provides flexibility with  
signal integrity of the signal before the ReDriver.  
à Adjustable Receiver Equalization  
à Independent Analog Output Swing Adjustment  
à Independent Analog Output Emphasis Control  
à Independent Channel Power Down Control  
A low-level input signal detection and output squelch function is  
provided for each channel. Each channel operates fully indepen-  
dently. When the channels are enabled (x_EN=1) and operating,  
that channels input signal level (on xI+/-) determines whether  
the output is active. If the input signal level of the channel falls  
below the active threshold level (Vth-) then the outputs are  
driven to the common mode voltage.  
ÎLow Power (220mW per Channel)  
ÎStand-by Mode – Power Down State  
ÎSupply Voltage: 3.3V  
ÎPackaging (Pb-free & Green):  
à 20-TQFN (4x4mm)  
In addition to signal conditioning, when EN = 0, the device  
enters a low power standby mode.  
Pin Diagram (Top Side View)  
Standard Mode (MODE = 0)  
Block Diagram  
20 19 18 17 16  
1
15  
14  
13  
AI+  
AO+  
AO-  
2
3
4
5
AI-  
GND  
BO-  
GND  
BI-  
BI+  
GND  
8
Signal Detection  
12  
11  
BO+  
6
7
10  
9
CML  
CML  
xO+  
xO-  
xl+  
Enhanced Mode (MODE = 1)  
Limiting  
Amp  
Equalizer  
xl-  
2019181716  
GND  
- Repeated 2 times -  
1
AI+  
AI-  
A_EN#  
BO-  
15  
14  
13  
12  
AO+  
AO-  
B_EN#  
BI-  
EMx  
2
3
4
5
X_EN#  
EN  
x_EQ  
x_EM  
Power  
Control  
Circuit  
Management  
11  
BO+  
BI+  
6
7 8 9 10  
www.pericom.comꢀ  
PS9016Bꢀ  
03/02/10ꢀ  
10-0118  
1

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