A product Line of
Diodes Incorporated
PI3EQX6801A
6.5Gbps, 1-port, 1.5V/3.3V SATA/SAS ReDriver™ with Analog/Digital Configuration
Features
Description
ꢀÎTwo 6.5Gbps differential channels
ꢀÎOutput swing up to 1.2V pk-to-pk
ꢀÎSAS, SATA fully supported
ꢀÎAdjustable Receiver Equalization - 0 to 16 dB
ꢀÎ100Ω Differential CML I/O’s
ꢀÎContinuous step output swing adjustment
ꢀÎContinuous step output pre-emphasis control
ꢀÎInput signal level detect and squelch for each channel
ꢀÎOOB fully supported
ꢀÎAuto HDD Rate Detection for out swing/emphasis setting
ꢀÎSupply Voltage: 1.5V or 3.3V
ꢀÎLow Power, 162mW @ 1.5V (600 mV Swing)
ꢀÎStand-by Mode – Power Down State: Current < 56 µA
ꢀÎAuto Slumber Mode power: 22.5mW typical
ꢀÎIndustrial Temperature Range -40 to 85°C
ꢀÎPackaging: 20-contact TQFN (4x4mm)
e PI3EQX6801A is a low power, 1.5V/3.3V, 6.5Gbps, SATA/SAS
signal ReDriver™. e device provides programmable equaliza-
tion, to optimize performance over a variety of physical mediums
by reducing Inter-Symbol Interference.
PI3EQX6801A supports two 100Ω Differential CML data I/O’s
between the Protocol ASIC to a switch fabric, across a backplane,
or to extend the signals across other distant data pathways on the
user’s platform.
e integrated equalization circuitry provides flexibility with
signal integrity of the signal before the ReDriver.
A low-level input signal detection and output squelch function is
provided for each channel. Each channel operates fully indepen-
dently. When the channels are enabled (x_EN#=0) and operating,
that channels input signal level (on xI+/-) determines whether the
output is active. If the input signal level of the channel falls below
the active threshold level (Vth-) then the outputs are driven to the
common mode voltage.
Each lane can be powered-down if x_EN# =1, and when A_EN# and
B_EN# are both high, the device enters a low power standby mode.
Pin Diagram (Top Side View)
Applications
ꢀÎServer
For V
DD
= 1.5V
ꢀÎDesktop
2019181716
GND
ꢀÎData Storage/Workstation
1
AI+
15
14
AO+
AO-
AI-
A_EN#
BO-
2
3
4
5
13
12
B_EN#
BI-
Block Diagram
11
BO+
BI+
Signal Detection
6
7 8 9 10
CML
CML
For V
DD
= 3.3V
+
XO
+
XI
Limiting
Amp
Equalizer
2019181716
GND
1
AI+
AI-
–
15
14
AO+
AO-
XI
–
XO
2
3
4
5
A_EN#
BO-
x_EQ
13
12
B_EN#
BI-
x_EM
x_OS
11
BO+
BI+
6
7 8 9 10
Power
x_EN#
Management
- Repeated 2 times -
www.diodes.com
January 2018
Diodes Incorporated
PI3EQX6801A
Document Number DS40631 Rev 1-2
1