Datasheet > PHP50N06

PHP50N06

更新时间： 2024-10-01 22:44:27

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管
页数	文件大小	规格书
7页	56K
描述
PowerMOS transistor

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PHP50N06 数据手册

Philips Semiconductors

Product specification

PowerMOS transistor

PHP50N06

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

field-effect power transistor in a

plastic envelope.

The device is intended for use in

Switched Mode Power Supplies

(SMPS), motor control, welding,

DC/DC and AC/DC converters,

and in automotive and general

purpose switching applications.

SYMBOL PARAMETER

MAX.

UNIT

V_DS

I_D

Drain-source voltage

Drain current (DC)

Total power dissipation

Junction temperature

Drain-source on-state

resistance

150

175

0.028

˚C

Ω

P_tot

T_j

R_DS(ON)

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

DESCRIPTION

tab

gate

drain

source

tab drain

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_DGR

±V_GS

I_D

Drain-source voltage

Drain-gate voltage

R_GS= 20 kΩ

Gate-source voltage

Drain current (DC)

Drain current (pulse peak value)

Total power dissipation

Storage temperature

Junction temperature

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

208

150

175

I_D

I_DM

P_tot

T_stg

T_j

- 55

˚C

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

Thermal resistance junction to

1.0

K/W

mounting base

R_{th j-a}

Thermal resistance junction to

ambient

K/W

August 1996

Rev 1.000

12 3 4 5 6 7

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