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PHP55N03LT PDF预览

PHP55N03LT

更新时间: 2024-02-19 22:25:53
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管
页数 文件大小 规格书
11页 109K
描述
N-channel TrenchMOS transistor Logic level FET

PHP55N03LT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TO-220AB包装说明:PLASTIC, SC-46, 3 PIN
针数:3Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.83
雪崩能效等级(Eas):60 mJ外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:25 V
最大漏极电流 (Abs) (ID):55 A最大漏极电流 (ID):55 A
最大漏源导通电阻:0.018 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码:TO-220ABJESD-30 代码:R-PSFM-T3
JESD-609代码:e3元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
最高工作温度:175 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:FLANGE MOUNT
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):85 W最大脉冲漏极电流 (IDM):220 A
认证状态:Not Qualified子类别:FET General Purpose Power
表面贴装:NO端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子位置:SINGLE
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

PHP55N03LT 数据手册

 浏览型号PHP55N03LT的Datasheet PDF文件第2页浏览型号PHP55N03LT的Datasheet PDF文件第3页浏览型号PHP55N03LT的Datasheet PDF文件第4页浏览型号PHP55N03LT的Datasheet PDF文件第5页浏览型号PHP55N03LT的Datasheet PDF文件第6页浏览型号PHP55N03LT的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
N-channel TrenchMOS transistor  
Logic level FET  
PHP55N03LT, PHB55N03LT  
PHD55N03LT  
FEATURES  
SYMBOL  
QUICK REFERENCE DATA  
d
’Trench’ technology  
• Very low on-state resistance  
• Fast switching  
• Low thermal resistance  
• Logic level compatible  
VDSS = 25 V  
ID = 55 A  
R
DS(ON) 14 m(VGS = 10 V)  
g
RDS(ON) 18 m(VGS = 5 V)  
s
GENERAL DESCRIPTION  
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.  
Applications:-  
• High frequency computer motherboard d.c. to d.c. converters  
• High current switching  
The PHP55N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.  
The PHB55N03LT is supplied in the SOT404 (D2PAK) surface mounting package.  
The PHD55N03LT is supplied in the SOT428 (DPAK)surface mounting package.  
PINNING  
SOT78 (TO220AB)  
SOT404 (D2PAK)  
SOT428 (DPAK)  
tab  
tab  
PIN  
1
DESCRIPTION  
tab  
gate  
2
drain 1  
source  
2
2
3
1 2 3  
1
3
1
3
tab drain  
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDSS  
VDGR  
VGS  
Drain-source voltage  
Tj = 25 ˚C to 175˚C  
Tj = 25 ˚C to 175˚C; RGS = 20 k  
-
-
-
-
25  
25  
± 15  
V
V
V
V
Drain-gate voltage  
Gate-source voltage (DC)  
Gate-source voltage (pulse  
peak value)  
VGSM  
Tj 150˚C  
± 20  
ID  
Drain current (DC)  
Tmb = 25 ˚C  
Tmb = 100 ˚C  
Tmb = 25 ˚C  
-
-
-
55  
38  
220  
A
A
A
IDM  
Drain current (pulse peak  
value)  
Ptot  
Tj, Tstg  
Total power dissipation  
Operating junction and  
storage temperature  
Tmb = 25 ˚C  
-
103  
175  
W
˚C  
- 55  
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.  
October 1999  
1
Rev 1.200  

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