PHP5N40

更新时间： 2024-02-22 23:43:04

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恩智浦 - NXP		晶体晶体管
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描述
PowerMOS transistor

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PHP5N40 数据手册

Philips Semiconductors

Product specification

PowerMOS transistor

PHP5N40

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

field-effect power transistor in a

plastic envelope featuring high

avalanche energy capability, stable

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

Drain-source voltage

Drain current (DC)

Total power dissipation

Drain-source on-state resistance

400

7.2

125

Ω

off-state

characteristics,

fast

P_tot

switching and high thermal cycling

performance with low thermal

resistance. Intended for use in

Switched Mode Power Supplies

(SMPS), motor control circuits and

R_DS(ON)

general

applications.

purpose

switching

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

DESCRIPTION

tab

gate

drain

source

tab drain

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

I_D

Continuous drain current

T_mb= 25 ˚C; V_GS= 10 V

T_mb= 100 ˚C; V_GS= 10 V

T_mb= 25 ˚C

7.2

4.6

I_DM

P_D

Pulsed drain current

Total dissipation

T_mb= 25 ˚C

125

∆P_D/∆T_mbLinear derating factor

T_mb> 25 ˚C

W/K

V_GS

E_AS

Gate-source voltage

Single pulse avalanche

energy

± 30

290

_DD≤ 50 V; starting T_j= 25˚C; R_GS= 50 Ω;

V_GS= 10 V

_DD≤ 50 V; starting T_j= 25˚C; R_GS= 50 Ω;

V_GS= 10 V

I_AS

Peak avalanche current

5.5

T_j, T_stg

Operating junction and

storage temperature range

- 55

150

˚C

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

Thermal resistance junction to

K/W

mounting base

R_{th j-a}

Thermal resistance junction to

ambient

K/W

February 1997

Rev 1.000

12 3 4 5 6 7

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