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PHB191NQ06LT

更新时间: 2024-01-23 03:46:23
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管功率场效应晶体管开关脉冲
页数 文件大小 规格书
13页 90K
描述
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology

PHB191NQ06LT 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SMALL OUTLINE, R-PSSO-G2Reach Compliance Code:not_compliant
风险等级:5.75Is Samacsys:N
雪崩能效等级(Eas):560 mJ外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:55 V
最大漏极电流 (ID):75 A最大漏源导通电阻:0.0044 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSSO-G2
JESD-609代码:e3湿度敏感等级:1
元件数量:1端子数量:2
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):245极性/信道类型:N-CHANNEL
最大脉冲漏极电流 (IDM):240 A表面贴装:YES
端子面层:Tin (Sn)端子形式:GULL WING
端子位置:SINGLE处于峰值回流温度下的最长时间:30
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

PHB191NQ06LT 数据手册

 浏览型号PHB191NQ06LT的Datasheet PDF文件第2页浏览型号PHB191NQ06LT的Datasheet PDF文件第3页浏览型号PHB191NQ06LT的Datasheet PDF文件第4页浏览型号PHB191NQ06LT的Datasheet PDF文件第6页浏览型号PHB191NQ06LT的Datasheet PDF文件第7页浏览型号PHB191NQ06LT的Datasheet PDF文件第8页 
PHP/PHB191NQ06LT  
N-channel TrenchMOS™ logic level FET  
Philips Semiconductors  
6. Characteristics  
Table 5:  
Characteristics  
Tj = 25 °C unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max Unit  
Static characteristics  
V(BR)DSS drain-source breakdown voltage  
ID = 250 µA; VGS = 0 V  
Tj = 25 °C  
55  
50  
-
-
-
-
V
V
Tj = 55 °C  
VGS(th)  
gate-source threshold voltage  
drain-source leakage current  
ID = 1 mA; VDS = VGS; Figure 9 and 10  
Tj = 25 °C  
1
1.5  
2
V
V
V
Tj = 175 °C  
0.5  
-
-
-
-
Tj = 55 °C  
2.2  
IDSS  
VDS = 55 V; VGS = 0 V  
Tj = 25 °C  
-
-
-
-
1
µA  
µA  
nA  
Tj = 175 °C  
-
500  
100  
IGSS  
gate-source leakage current  
VGS = ±15 V; VDS = 0 V  
VGS = 10 V; ID = 25 A; Figure 7 and 8  
Tj = 25 °C  
2
RDSon  
drain-source on-state resistance  
-
-
-
-
3.1  
-
3.7  
7.4  
4.2  
4.4  
mΩ  
mΩ  
mΩ  
mΩ  
Tj = 175 °C  
VGS = 5 V; ID = 25 A; Figure 7 and 8  
VGS = 4.5 V; ID = 25 A; Figure 8  
3.5  
-
Dynamic characteristics  
Qg(tot)  
Qgs  
Qgd  
Ciss  
Coss  
Crss  
td(on)  
tr  
total gate charge  
gate-source charge  
gate-drain (Miller) charge  
input capacitance  
output capacitance  
reverse transfer capacitance  
turn-on delay time  
rise time  
ID = 25 A; VDD = 44 V; VGS = 5 V; Figure 13  
-
-
-
-
-
-
-
-
-
-
95.6  
17.2  
37.6  
7665  
1045  
465  
63  
-
-
-
-
-
-
-
-
-
-
nC  
nC  
nC  
pF  
pF  
pF  
ns  
ns  
ns  
ns  
VGS = 0 V; VDS = 25 V; f = 1 MHz;  
Figure 11  
VDD = 30 V; RL = 1.2 ;  
VGS = 5 V; RG = 10 Ω  
232  
273  
178  
td(off)  
tf  
turn-off delay time  
fall time  
Source-drain diode  
VSD  
trr  
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12  
-
-
-
0.79 1.2  
V
reverse recovery time  
recovered charge  
IS = 20 A; dIS/dt = 100 A/µs; VGS = 0 V  
78  
-
-
ns  
nC  
Qr  
171  
9397 750 13168  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 01 — 05 May 2004  
5 of 13  

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