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PCS2I3805EG-20-AR PDF预览

PCS2I3805EG-20-AR

更新时间: 2024-11-01 07:03:35
品牌 Logo 应用领域
PULSECORE 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 193K
描述
3.3V CMOS Dual 1-To-5 Clock Driver

PCS2I3805EG-20-AR 技术参数

生命周期:Obsolete包装说明:0.209 INCH, GREEN, SSOP-20
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:N系列:3805
输入调节:DIFFERENTIAL LATCHEDJESD-30 代码:R-PDSO-G20
长度:7.2 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:2反相输出次数:
端子数量:20实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):2.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:5.3 mmBase Number Matches:1

PCS2I3805EG-20-AR 数据手册

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September 2006  
rev 0.3  
PCS2P3805E  
3.3V CMOS Dual 1-To-5 Clock Driver  
Functional Description  
Features  
Advanced CMOS Technology  
The PCS2P3805E is a 3.3V clock driver built using  
advanced CMOS technology. The device consists of two  
banks of drivers, each with a 1:5 fanout and its own output  
enable control. The device has a "heartbeat" monitor for  
diagnostics and PLL driving. The MON output is identical to  
all other outputs and complies with the output specifications  
in this document. The PCS2P3805E offers low capacitance  
inputs. The PCS2P3805E is designed for high speed clock  
distribution where signal quality and skew are critical. The  
PCS2P3805E also allows single point-to-point transmission  
line driving in applications such as address distribution,  
where one signal must be distributed to multiple receivers  
with low skew and high signal quality.  
Guaranteed low skew < 200pS (max)  
Very low propagation delay < 2.5nS (max)  
Very low duty cycle distortion < 270pS (max)  
Very low CMOS power levels  
Operating frequency up to 166MHz  
TTL compatible inputs and outputs  
Inputs can be driven from 3.3V or 5V components  
Two independent output banks with 3-state control  
1:5 fanout per bank  
"Heartbeat" monitor output  
VCC = 3.3V ± 0.3V  
Available in SSOP and QSOP Packages  
Block Diagram  
Pin Diagram  
20  
VCCA  
OA1  
VCCB  
1
2
OEA  
INA  
19  
18  
17  
16  
15  
OB1  
OB2  
OB3  
5
OA1 – OA5  
OA2  
3
4
OA3  
5
6
GNDA  
GNDB  
OB4  
PCS2P3805E  
5
INB  
OB1 – OB5  
MON  
OA4  
OA5  
14  
13  
12  
11  
7
OB5  
OEB  
GNDQ  
8
9
MON  
OEB  
OEA  
INA  
10  
INB  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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