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PCA9703HF,118 PDF预览

PCA9703HF,118

更新时间： 2024-11-14 21:14:15
品牌 Logo 应用领域
恩智浦 - NXP PC
页数 文件大小 规格书
27页 264K
描述
PCA9703 - 18 V tolerant SPI 16-bit GPI with maskable INT QFN 24-Pin

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PCA9703HF,118 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：QCCN, LCC24,.16SQ,20
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：S-PQCC-N24JESD-609代码：e3
最大频率@ Nom-Sup：5000000 Hz湿度敏感等级：1
位数：16功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC24,.16SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified子类别：Shift Registers
标称供电电压 (Vsup)：5 V表面贴装：YES
温度等级：AUTOMOTIVE端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

PCA9703HF,118 数据手册

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PCA9703  
18 V tolerant SPI 16-bit GPI with maskable INT  
Rev. 2 — 14 June 2012  
Product data sheet  
1. General description  
The PCA9703 is a low power 18 V tolerant SPI General Purpose Input (GPI) shift register  
designed to monitor the status of switch inputs. It generates an interrupt when one or  
more of the switch inputs change state but allows selected inputs to not generate  
interrupts using the interrupt masking feature. The input level is recognized as a HIGH  
when it is greater than 0.8 × VDD and as a LOW when it is less than 0.55 × VDD (minimum  
LOW threshold of 2.5 V at 5 V node). The PCA9703 can monitor up to 16 switch inputs.  
The falling edge of the CS pin samples the input port status and clears the interrupt. When  
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of  
the shift register. The serial input is sampled on the falling edge of SCLK. The contents of  
the shift register are loaded into the interrupt mask register of the device on the rising  
edge of CS.  
Each of the input ports has a 18 V breakdown ESD protection circuit, which dumps the  
ESD/overvoltage current to ground. When used with a series resistor (minimum 100 kΩ),  
the input can connect to a 12 V battery and support double battery, reverse battery, 27 V  
jump start and 40 V load dump conditions in automotive applications. Higher voltages can  
be tolerated on the inputs depending on the series resistor used to limit the input current.  
The INT_EN pin is used to both enable the GPI pins and to enable the INT output pin to  
minimize battery drain in cyclically supplied pull-up or pull-down applications. The SDIN  
pull-down prevents floating nodes when the device is used in daisy-chain applications.  
With both the high breakdown voltage and high ESD, this device is useful for both  
automotive (AEC-Q100 compliance available) and mobile applications.  
2. Features and benefits  
16 general purpose input ports  
18 V tolerant input ports with 100 kΩ external series resistor  
Input LOW threshold 0.55 × VDD with minimum of 2.5 V at VDD = 4.5 V  
Input hysteresis 0.04 × VDD with minimum of 180 mV at VDD = 4.5 V  
Open-drain interrupt output  
Interrupt enable pin (INT_EN) disables GPI pins and interrupt output  
Interrupt-masking feature allows no interrupt generation from selected inputs  
VDD range: 4.5 V to 5.5 V  
IDD is very low 2.5 μA maximum  
SPI serial interface with speeds up to 5 MHz  
SPI supports daisy-chain connection for large switch numbers  
AEC-Q100 compliance available  
 
 
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