Datasheet > PCA9547BS

PCA9547BS

更新时间： 2024-09-18 04:54:07

品牌	Logo	应用领域
德州仪器 - TI		复用器逻辑集成电路
页数	文件大小	规格书
26页	141K
描述
8-channel I2C-bus multiplexer with reset

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PCA9547BS 数据手册

PCA9547

8-channel I²C-bus multiplexer with reset

Rev. 02 — 12 September 2006

Product data sheet

1. General description

The PCA9547 is an octal bidirectional translating multiplexer controlled by the I²C-bus.

The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one

SCx/SDx channel can be selected at a time, determined by the contents of the

programmable control register. The device powers up with Channel 0 connected, allowing

immediate communication between the master and downstream devices on that channel.

An active LOW reset input allows the PCA9547 to recover from a situation where one of

the downstream I²C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the

I²C-bus state machine causing all the channels to be deselected, except Channel 0 so

that the master can regain control of the bus.

The pass gates of the multiplexers are constructed such that the V_DDpin can be used to

limit the maximum high voltage which will be passed by the PCA9547. This allows the use

of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate

with 5 V parts without any additional protection. External pull-up resistors pull the bus up

to the desired voltage level for each channel. All I/O pins are 5 V tolerant.

2. Features

I 1-of-8 bidirectional translating multiplexer

I I²C-bus interface logic; compatible with SMBus standards

I Active LOW RESET input

I 3 address pins allowing up to 8 devices on the I²C-bus

I Channel selection via I²C-bus, one channel at a time

I Power-up with all channels deselected except Channel 0 which is connected

I Low R_onmultiplexers

I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses

I No glitch on power-up

I Supports hot insertion

I Low standby current

I Operating power supply voltage range of 2.3 V to 5.5 V

I 5 V tolerant inputs

I 0 Hz to 400 kHz clock frequency

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

I Packages offered: SO24, TSSOP24, HVQFN24

12 3 4 5 6 7...26

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