AM1802
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SPRS710–NOVEMBER 2010
AM1802 ARM Microprocessor
Check for Samples: AM1802
1 AM1802 ARM Microprocessor
1.1 Features
12
•
•
NAND (8-/16-Bit-Wide Data)
16-Bit SDRAM With 128 MB Address
Space
• Highlights
– 300-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
– DDR2/Mobile DDR Memory Controller
•
16-Bit DDR2 SDRAM With 512 MB
Address Space or
16-Bit mDDR SDRAM With 256 MB
Address Space
•
• Three Configurable 16550 type UART Modules:
– With Modem Control Signals
– 16-byte FIFO
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
– 16x or 13x Oversampling Option
• Two Serial Peripheral Interfaces (SPI) Each
With Multiple Chip-Selects
• One Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Interfaces
• One Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
• USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– One Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– One Multichannel Audio Serial Port
– 10/100 Mb/s Ethernet MAC (EMAC)
– Three 64-Bit General-Purpose Timers
– One 64-bit General-Purpose/Watchdog Timer
• 300-MHz ARM926EJ-S™ RISC MPU
• ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) Rx and Tx
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
• One Multichannel Audio Serial Port:
– Transmit/Receive Clocks
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable
– 2 Channel Controllers
– 3 Transfer Controllers
– 64 Independent DMA Channels
– 16 Quick DMA Channels
– FIFO buffers for Transmit and Receive
• 10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant
– Programmable Transfer Burst Size
• 128K-Byte On-chip Memory
• 1.8V or 3.3V LVCMOS IOs (except for USB and
DDR2 interfaces)
• Two External Memory Interfaces:
– EMIFA
– MII Media Independent Interface
– RMII Reduced Media Independent Interface
– Management Data I/O (MDIO) Module
• Real-Time Clock With 32 KHz Oscillator and
Separate Power Rail
• Three One 64-Bit General-Purpose Timers
(Each configurable as Two 32-Bit Timers)
•
NOR (8-/16-Bit-Wide Data)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
ARM926EJ-S is a trademark of ARM Limited.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated