AM1806
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SPRS658B–FEBRUARY 2010–REVISED MAY 2010
AM1806 ARM Microprocessor
Check for Samples: AM1806
1 AM1806 ARM Microprocessor
1.1 Features
12
– With Modem Control Signals
• Highlights
– 16-byte FIFO
– 16x or 13x Oversampling Option
• Two Serial Peripheral Interfaces (SPI) Each
With Multiple Chip-Selects
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Interfaces
• Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem
(PRUSS)
– 375/456-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Programmable Real-Time Unit Subsystem
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
– Two Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– One Multichannel Audio Serial Port
– Two Independent Programmable Realtime
Unit (PRU) Cores
– Three 64-Bit General-Purpose Timers
– One 64-bit General-Purpose/Watchdog Timer
– TwoEnhanced Pulse Width Modulators
– Three 32-Bit Enhanced Capture Modules
• 375/456-MHz ARM926EJ-S™ RISC MPU
•
•
•
•
32-Bit Load/Store RISC architecture
4K Byte instruction RAM per core
512 Bytes data RAM per core
PRU Subsystem (PRUSS) can be disabled
via software to save power
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
•
Register 30 of each PRU is exported from
the subsystem in addition to the normal
R31 output of the PRU cores.
– 2 Channel Controllers
– 3 Transfer Controllers
– Standard power management mechanism
– 64 Independent DMA Channels
– 16 Quick DMA Channels
– Programmable Transfer Burst Size
•
•
Clock gating
Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
• USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
• 1.8V or 3.3V LVCMOS IOs (except for USB and
DDR2 interfaces)
• Two External Memory Interfaces:
– EMIFA
•
•
•
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
16-Bit SDRAM With 128 MB Address
Space
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) Rx and Tx
– DDR2/Mobile DDR Memory Controller
• One Multichannel Audio Serial Port:
– Transmit/Receive Clocks
•
16-Bit DDR2 SDRAM With 512 MB
Address Space or
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable
•
16-Bit mDDR SDRAM With 256 MB
Address Space
• Three Configurable 16550 type UART Modules:
– FIFO buffers for Transmit and Receive
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
ARM926EJ-S is a trademark of ARM Limited.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright © 2010, Texas Instruments Incorporated
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