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PAM1806BZWT4

更新时间： 2024-11-08 05:59:31
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路uCs集成电路uPs集成电路微处理器
页数 文件大小 规格书
241页 1566K
描述
AM1806 ARM Microprocessor

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PAM1806BZWT4 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：GREEN, PLASTIC, NFBGA-361针数：361
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.84Is Samacsys：N
其他特性：IT ALSO OPERATES IN 0.95V MINIMUM SUPPLYJESD-30 代码：S-PBGA-B361
长度：16 mm端子数量：361
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
认证状态：Not Qualified座面最大高度：1.4 mm
最大供电电压：1.35 V最小供电电压：1.25 V
标称供电电压：1.3 V表面贴装：YES
技术：CMOS端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
宽度：16 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

PAM1806BZWT4 数据手册

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AM1806  
www.ti.com  
SPRS658–FEBRUARY 2010  
AM1806 ARM Microprocessor  
Check for Samples: AM1806  
1 AM1806 ARM Microprocessor  
1.1 Features  
12  
via software to save power  
• 375/456-MHz ARM926EJ-S™ RISC MPU  
•
Register 30 of each PRU is exported from  
the subsystem in addition to the normal  
R31 output of the PRU cores.  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
– 2 Channel Controllers  
– 3 Transfer Controllers  
– 64 Independent DMA Channels  
– 16 Quick DMA Channels  
– Programmable Transfer Burst Size  
– Standard power management mechanism  
•
•
Clock gating  
Entire subsystem under a single PSC  
clock gating domain  
– Dedicated interrupt controller  
– Dedicated switched central resource  
• USB 2.0 OTG Port With Integrated PHY (USB0)  
– USB 2.0 High-/Full-Speed Client  
– USB 2.0 High-/Full-/Low-Speed Host  
– End Point 0 (Control)  
– End Points 1,2,3,4 (Control, Bulk, Interrupt or  
ISOC) Rx and Tx  
• One Multichannel Audio Serial Port:  
– Transmit/Receive Clocks  
• 1.8V or 3.3V LVCMOS IOs (except for USB and  
DDR2 interfaces)  
• Two External Memory Interfaces:  
– EMIFA  
•
•
•
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
16-Bit SDRAM With 128 MB Address  
Space  
– DDR2/Mobile DDR Memory Controller  
•
16-Bit DDR2 SDRAM With 512 MB  
Address Space or  
– Two Clock Zones and 16 Serial Data Pins  
– Supports TDM, I2S, and Similar Formats  
– DIT-Capable  
•
16-Bit mDDR SDRAM With 256 MB  
Address Space  
• Three Configurable 16550 type UART Modules:  
– With Modem Control Signals  
– 16-byte FIFO  
– FIFO buffers for Transmit and Receive  
• Two Multichannel Buffered Serial Ports:  
– Transmit/Receive Clocks  
– 16x or 13x Oversampling Option  
• Two Serial Peripheral Interfaces (SPI) Each  
With Multiple Chip-Selects  
– Two Clock Zones and 16 Serial Data Pins  
– Supports TDM, I2S, and Similar Formats  
– AC97 Audio Codec Interface  
• Two Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
Interfaces  
– Telecom Interfaces (ST-Bus, H100)  
– 128-channel TDM  
– FIFO buffers for Transmit and Receive  
• Video Port Interface (VPIF):  
• Two Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
– Two 8-bit SD (BT.656), Single 16-bit or Single  
Raw (8-/10-/12-bit) Video Capture Channels  
– Two 8-bit SD (BT.656), Single 16-bit Video  
Display Channels  
• One Host-Port Interface (HPI) With 16-Bit-Wide  
Muxed Address/Data Bus For High Bandwidth  
• Programmable Real-Time Unit Subsystem  
(PRUSS)  
• Universal Parallel Port (uPP):  
– Two Independent Programmable Realtime  
Unit (PRU) Cores  
– High-Speed Parallel Interface to FPGAs and  
Data Converters  
– Data Width on Each of Two Channels is 8- to  
16-bit Inclusive  
•
•
•
•
32-Bit Load/Store RISC architecture  
4K Byte instruction RAM per core  
512 Bytes data RAM per core  
– Single Data Rate or Dual Data Rate Transfers  
PRU Subsystem (PRUSS) can be disabled  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
ARM926EJ-S is a trademark of ARM Limited.  
ADVANCE INFORMATION concerns new products in the sampling  
or preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
Copyright © 2010, Texas Instruments Incorporated  
 
 
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