Datasheet > PALCE16V8Q-20PC5

PALCE16V8Q-20PC5

更新时间： 2024-11-07 23:10:51

品牌	Logo	应用领域
超微 - AMD		/
页数	文件大小	规格书
26页	221K
描述
EE CMOS 20-Pin Universal Programmable Array Logic

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中文翻译

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数据手册

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PALCE16V8Q-20PC5 数据手册

FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25

IND: H-10/15/25, Q-20/25

PALCE16V8 Family

EE CMOS 20-Pin Universal Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

■ Pin and function compatible with all 20-pin

■ Programmable output polarity

GAL devices

■ Programmable enable/disable control

■ Preloadable output registers for testability

■ Automatic register reset on power up

■ Electrically erasable CMOS technology

provides reconfigurable logic and full

testability

■ Cost-effective 20-pin plastic DIP, PLCC, and

■ High-speed CMOS technology

SOIC packages

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

■ Extensive third-party software and programmer

support through FusionPLD partners

■ Direct plug-in replacement for the PAL16R8

■ Fully tested for 100% programming and

series and most of the PAL10H8 series

functional yields and high reliability

■ Outputs programmable as registered or

■ 5 ns version utilizes a split leadframe for

combinatorial in any combination

improved performance

■ Peripheral Component Interconnect (PCI)

compliant

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with

low-power, high-speed, electrically-erasable CMOS

technology. It is functionally compatible with all 20-pin

GALdevices. Themacrocellsprovideauniversaldevice

architecture. The PALCE16V8 will directly replace the

PAL16R8 and PAL10H8 series devices, with the excep-

tion of the PAL16C1.

The fixed OR array allows up to eight data product terms

per output for logic functions. The sum of these products

feeds the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial with an active-

high or active-low output. The output configuration is

determined by two global bits and one local bit

controlling four multiplexers in each macrocell.

The PALCE16V8 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced to

sum-of-products form, taking advantage of the very

wide input gates available in PAL devices. The equa-

tions are programmed into the device through floating-

gate cells in the AND logic array that can be erased

electrically.

AMD’s FusionPLD program allows PALCE16V8 de-

signs to be implemented using a wide variety of popular

industry-standard design tools. By working closely with

the FusionPLD partners, AMD certifies that the tools

provideaccurate, qualitysupport. Byensuringthatthird-

party tools are available, costs are lowered because a

designer does not have to buy a complete set of new

tools for each device. The FusionPLD program also

greatly reduces design time since a designer can use a

tool that is already installed and familiar.

Publication# 16493 Rev. D Amendment/0

Issue Date: February 1996

2-36

12 3 4 5 6 7...26

中文翻译

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与PALCE16V8Q-20PC5相关器件

型号	品牌	获取价格	描述	数据表
PALCE16V8Q-20PI	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20PI/4	LATTICE	获取价格	EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20PI4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20PI5	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20SC	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20SC4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20SC5	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20SI	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20SI4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-20SI5	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic

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