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PALCE16V8Q-25JC/4 PDF预览

PALCE16V8Q-25JC/4

更新时间: 2024-11-07 22:28:07
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
32页 611K
描述
EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic

PALCE16V8Q-25JC/4 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.61架构:PAL-TYPE
最大时钟频率:37 MHzJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.9662 mm
湿度敏感等级:1专用输入次数:8
I/O 线路数量:8输入次数:18
输出次数:8产品条款数:64
端子数量:20最高工作温度:75 °C
最低工作温度:组织:8 DEDICATED INPUTS, 8 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:5 V可编程逻辑类型:EE PLD
传播延迟:25 ns认证状态:Not Qualified
座面最大高度:4.572 mm子类别:Programmable Logic Devices
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:8.9662 mmBase Number Matches:1

PALCE16V8Q-25JC/4 数据手册

 浏览型号PALCE16V8Q-25JC/4的Datasheet PDF文件第2页浏览型号PALCE16V8Q-25JC/4的Datasheet PDF文件第3页浏览型号PALCE16V8Q-25JC/4的Datasheet PDF文件第4页浏览型号PALCE16V8Q-25JC/4的Datasheet PDF文件第5页浏览型号PALCE16V8Q-25JC/4的Datasheet PDF文件第6页浏览型号PALCE16V8Q-25JC/4的Datasheet PDF文件第7页 
PALCE16V8  
COML:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25  
IND:-12/15/25  
PALCE16V8Z COML:-25  
PALCE16V8 and PALCE16V8Z Families  
EE CMOS (Zero-Power) 20-Pin Universal  
Programmable Array Logic  
DISTINCTIVE CHARACTERISTICS  
®
  Pin and function compatible w ith all 20-pin PAL devices  
  Electrically erasable CMOS technology provides reconfigurable logic and full testability  
  High-speed CMOS technology  
— 5-ns propagation delay for “-5” version  
— 7.5-ns propagation delay for “-7” version  
  Direct plug-in replacement for the PAL16R8 series  
  Outputs programmable as registered or combinatorial in any combination  
  Peripheral Component Interconnect (PCI) compliant  
  Programmable output polarity  
  Programmable enable/disable control  
  Preloadable output registers for testability  
  Automatic register reset on pow er up  
  Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages  
  Extensive third-party softw are and programmer support  
  Fully tested for 100% programming and functional yields and high reliability  
  5-ns version utilizes a split leadframe for improved performance  
GENERAL DESCRIPTION  
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-  
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The  
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the  
PAL16R8, with the exception of the PAL16C1.  
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby  
current, the PALCE16V8Z allows battery-powered operation for an extended period.  
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to  
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic  
can always be reduced to sum-of-products form, taking advantage of the very wide input gates  
available in PAL devices. The equations are programmed into the device through floating-gate  
cells in the AND logic array that can be erased electrically.  
The fixed OR array allows up to eight data product terms per output for logic functions. The  
sum of these products feeds the output macrocell. Each macrocell can be programmed as  
registered or combinatorial with an active-high or active-low output. The output configuration  
is determined by two global bits and one local bit controlling four multiplexers in each  
macrocell.  
Publication# 1 6493  
Amendment/0  
Rev: F  
Issue Date: September 2000  

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