Datasheet > PALCE16V8Q-25JI

PALCE16V8Q-25JI

更新时间： 2024-11-07 23:10:51

品牌	Logo	应用领域
超微 - AMD		/
页数	文件大小	规格书
26页	221K
描述
EE CMOS 20-Pin Universal Programmable Array Logic

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

PALCE16V8Q-25JI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QLCC	包装说明：	QCCJ, LDCC20,.4SQ
针数：	20	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.71
其他特性：	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 1 EXTERNAL CLOCK	架构：	PAL-TYPE
最大时钟频率：	37 MHz	JESD-30 代码：	S-PQCC-J20
JESD-609代码：	e0	长度：	8.9662 mm
专用输入次数：	8	I/O 线路数量：	8
输入次数：	18	输出次数：	8
产品条款数：	64	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	8 DEDICATED INPUTS, 8 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC20,.4SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	25 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	8.9662 mm
Base Number Matches：	1

PALCE16V8Q-25JI 数据手册

FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25

IND: H-10/15/25, Q-20/25

PALCE16V8 Family

EE CMOS 20-Pin Universal Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

■ Pin and function compatible with all 20-pin

■ Programmable output polarity

GAL devices

■ Programmable enable/disable control

■ Preloadable output registers for testability

■ Automatic register reset on power up

■ Electrically erasable CMOS technology

provides reconfigurable logic and full

testability

■ Cost-effective 20-pin plastic DIP, PLCC, and

■ High-speed CMOS technology

SOIC packages

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

■ Extensive third-party software and programmer

support through FusionPLD partners

■ Direct plug-in replacement for the PAL16R8

■ Fully tested for 100% programming and

series and most of the PAL10H8 series

functional yields and high reliability

■ Outputs programmable as registered or

■ 5 ns version utilizes a split leadframe for

combinatorial in any combination

improved performance

■ Peripheral Component Interconnect (PCI)

compliant

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with

low-power, high-speed, electrically-erasable CMOS

technology. It is functionally compatible with all 20-pin

GALdevices. Themacrocellsprovideauniversaldevice

architecture. The PALCE16V8 will directly replace the

PAL16R8 and PAL10H8 series devices, with the excep-

tion of the PAL16C1.

The fixed OR array allows up to eight data product terms

per output for logic functions. The sum of these products

feeds the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial with an active-

high or active-low output. The output configuration is

determined by two global bits and one local bit

controlling four multiplexers in each macrocell.

The PALCE16V8 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced to

sum-of-products form, taking advantage of the very

wide input gates available in PAL devices. The equa-

tions are programmed into the device through floating-

gate cells in the AND logic array that can be erased

electrically.

AMD’s FusionPLD program allows PALCE16V8 de-

signs to be implemented using a wide variety of popular

industry-standard design tools. By working closely with

the FusionPLD partners, AMD certifies that the tools

provideaccurate, qualitysupport. Byensuringthatthird-

party tools are available, costs are lowered because a

designer does not have to buy a complete set of new

tools for each device. The FusionPLD program also

greatly reduces design time since a designer can use a

tool that is already installed and familiar.

Publication# 16493 Rev. D Amendment/0

Issue Date: February 1996

2-36

12 3 4 5 6 7...26

中文翻译

下载PDF

与PALCE16V8Q-25JI相关器件

型号	品牌	获取价格	描述	数据表
PALCE16V8Q-25JI/4	LATTICE	获取价格	EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25JI4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25JI5	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25PC	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25PC/4	LATTICE	获取价格	EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25PC4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25PC5	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25PI	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25PI/4	LATTICE	获取价格	EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
PALCE16V8Q-25PI4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic

与PALCE16V8Q-25JI相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

21
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

19
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

44
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

38

产品中心

服务支持

精选活动

关于我们

帮助中心

PALCE16V8Q-25JI

PALCE16V8Q-25JI 技术参数

PALCE16V8Q-25JI 数据手册

与PALCE16V8Q-25JI相关器件

与PALCE16V8Q-25JI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

PALCE16V8Q-25JI

PALCE16V8Q-25JI 技术参数

PALCE16V8Q-25JI 数据手册

与PALCE16V8Q-25JI相关器件

与PALCE16V8Q-25JI相关文章

您还可以找

您在本页遇到什么问题？