Datasheet > PALCE16V8H-7JC/5

PALCE16V8H-7JC/5

更新时间： 2024-09-19 22:22:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
32页	611K
描述
EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic

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PALCE16V8H-7JC/5 数据手册

PALCE16V8

COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25

IND:-12/15/25

PALCE16V8Z COM’L:-25

PALCE16V8 and PALCE16V8Z Families

EE CMOS (Zero-Power) 20-Pin Universal

Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible w ith all 20-pin PAL devices

Electrically erasable CMOS technology provides reconﬁgurable logic and full testability

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for the PAL16R8 series

Outputs programmable as registered or combinatorial in any combination

Peripheral Component Interconnect (PCI) compliant

Programmable output polarity

Programmable enable/disable control

Preloadable output registers for testability

Automatic register reset on pow er up

Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages

Extensive third-party softw are and programmer support

Fully tested for 100% programming and functional yields and high reliability

5-ns version utilizes a split leadframe for improved performance

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-

erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The

macrocells provide a universal device architecture. The PALCE16V8 will directly replace the

PAL16R8, with the exception of the PAL16C1.

The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby

current, the PALCE16V8Z allows battery-powered operation for an extended period.

The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to

implement complex logic functions easily and efﬁciently. Multiple levels of combinatorial logic

can always be reduced to sum-of-products form, taking advantage of the very wide input gates

available in PAL devices. The equations are programmed into the device through ﬂoating-gate

cells in the AND logic array that can be erased electrically.

The ﬁxed OR array allows up to eight data product terms per output for logic functions. The

sum of these products feeds the output macrocell. Each macrocell can be programmed as

registered or combinatorial with an active-high or active-low output. The output conﬁguration

is determined by two global bits and one local bit controlling four multiplexers in each

macrocell.

Publication# 1 6493

Amendment/0

Rev: F

Issue Date: September 2000

12 3 4 5 6 7...32

中文翻译

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PALCE16V8H-7JC/5 替代型号

型号	品牌	替代类型	描述	数据表
GAL16V8D-7LJI	LATTICE	完全替代	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-7LJN	LATTICE	类似代替	High Performance E2CMOS PLD Generic Array Log
GAL16V8D-7LJ	LATTICE	类似代替	High Performance E2CMOS PLD Generic Array Logic

与PALCE16V8H-7JC/5相关器件

型号	品牌	获取价格	描述	数据表
PALCE16V8H-7JC4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8H-7JC5	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8H-7JI	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8H-7JI4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8H-7JI5	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8H-7PC	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8H-7PC/5	LATTICE	获取价格	EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
PALCE16V8H-7PC4	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic
PALCE16V8H7PC5	ETC	获取价格	IC-CMOS EEPLD
PALCE16V8H-7PC5	AMD	获取价格	EE CMOS 20-Pin Universal Programmable Array Logic

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