Datasheet > P701-50DC

P701-50DC

更新时间： 2024-01-28 12:47:24

品牌	Logo	应用领域
PLL		/
页数	文件大小	规格书
6页	206K
描述
Low EMI Spread Spectrum Multiplier IC

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P701-50DC 数据手册

PLL701-50

Low EMI Spread Spectrum Multiplier IC

BLOCK DIAGRAM

FEATURES

•

Spread Spectrum Clock Generator/Multiplier with

output selectable from 1x to 8x.

REF

XIN/FIN

XOUT

PLL

SST

XTAL

OSC

•

13MHz to 224MHz output with output enable.

13MHz to 30 MHz input frequency from crystal or

external clock signal.

Reduced EMI from Spread Spectrum Modulation,

with selectable modulation magnitude for Center

Spread, Down Spread or Asymmetric Spread.

TTL/CMOS compatible outputs.

3.3V Operating Voltage.

150 ps maximum cycle-to-cycle jitter.

Available in 16-Pin 150mil SSOP.

FOUT

SC(0:3)

SD(0:1)

M(0:2)

Control

Logic

•

DIE PAD CONFIGURATION

69 mil

1700, 2540

AVDD

DESCRIPTION

XOUT/SD0*^

C501A

A2727

-27

The PLL701-50 is a low EMI Clock Generator and

Multiplier for high-speed digital systems. It uses

PhaseLink’s unique (Patent Pending) Spread

Spectrum Technology (SST) and permits different

levels of EMI reduction by selecting the amplitude of

the applied SST. The SST feature can be disabled.

The chip operates with input frequencies ranging from

13 to 30 MHz and provides 1x to 8x multiplication at

its output.

AVDD

GNDOSC

REF/SD1*^

VDD

VDD (optional)

M2^

M1^

M0^

VDD (optional)

SC3^

OE^

TESTB

OUTPUT CLOCK (FOUT) SELECTION

FOUT

SC0^

SC1^

FIN/XIN

(MHz)

FOUT

(MHz)

Multiplier

GNDBUF

13 ~ 28

14 ~ 30

13 ~ 28

20 ~ 30

17 ~ 30

15 ~ 30

13 ~ 28

26 ~ 56

42 ~ 90

52 ~ 112

100 ~ 150

102 ~ 180

105 ~ 210

104 ~ 224

DIE SPECIFICATIONS

Name

Value

Size

104 x 69 mil

GND

Reverse side

Pad dimensions

Thickness

80 micron x 80 micron

10 mil

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1

12 3 4 5 6

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