Datasheet > P702-25SCL

P702-25SCL

更新时间： 2024-01-12 19:24:30

品牌	Logo	应用领域
PLL		时钟
页数	文件大小	规格书
4页	205K
描述
Low EMI Spread Spectrum Multiplier Clock

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数据手册

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P702-25SCL 数据手册

PLL701-25

Low EMI Spread Spectrum Multiplier Clock

FEATURES

PIN CONFIGURATION

•

Spread Spectrum clock with frequency range of

FIN

CLK2

CLK1

GND

CLK5

CLK4

VDD

33 ~ 90MHz.

•

Output frequency 1X the input frequency.

Less than 250 ps skew between outputs.

Less than 100 ps cycle - cycle jitter.

±0.50% Center Spread Modulation (+/-15%

tolerance).

CLK3

•

TTL/CMOS compatible outputs.

3.3V operation.

Available in 8-Pin 150mil SOIC.

FIN = 33 ~ 90 Mhz

DESCRIPTION

The PLL701-25 is a Spread Spectrum Clock

Generator designed for the purpose of reducing EMI

in high-speed digital systems. The device is designed

to operate from 33 ~ 90MHz and provides five low-

skew outputs.

BLOCK DIAGRAM

CLK1

CLK2

CLK3

CLK4

CLK5

PLL SST

FIN

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/04/05 Page 1

12 3 4

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