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P702-01XC PDF预览

P702-01XC

更新时间: 2024-01-07 17:12:31
品牌 Logo 应用领域
PLL 时钟发生器PC
页数 文件大小 规格书
8页 271K
描述
Clock Generator for PowerPC Based Applications

P702-01XC 数据手册

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PLL702-01  
Clock Generator for PowerPC Based Applications  
FEATURES  
PIN ASSIGNMENT (28 pin SSOP)  
1 CPU Clock output with selectable frequencies (50,  
T
^
CPUDRV_SEL  
1
2
3
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CLK_SEL0  
66, 75, 80, 83, 90, 100,125 or 133 MHz).  
1 ASIC output clock (at CPU clock or CPU clock ÷ 2).  
2 ASIC output clocks (at CPU clock) w/ output enable.  
1 PCI output clock w/ output enable  
1 Selectable 48, 30 or 12MHz (USB) output.  
Selectable Spread Spectrum (SST) for EMI reduction  
on ASIC and CPU.  
PowerPC compatible output and drive CPU Clock.  
Selectable reduced 67% drive strength on CPU Clock  
Advanced, low power, sub-micron CMOS processes.  
14.31818MHz fundamental crystal input.  
3.3V and/or 2.5V operation.  
XIN  
ASIC2_OE*^  
VDD_ANA  
VDD_DIG  
T
CLK_SEL1  
^
SSC  
O
XOUT /  
^
SSC1  
GND_ANA  
GND_CP  
4
5
6
7
8
VDD_PC  
I
U
o
T
PCI / PCI_SEL*  
GND_PCI  
CP  
U
VDD_CP  
U
GND_USB  
9
VDD_ASIC1  
ASIC1  
VDD_USB  
10  
11  
12  
13  
14  
USB_SEL*T  
USB /  
GND_ASIC  
1
VDD_ASIC2  
ASIC2A  
^
ASIC1_SEL  
GND_DIG  
ASIC2  
B
GND_ASIC2  
^: Internal pull-up resistor  
*: Bi-directional pin  
: Tri-level input  
:
Note  
o
: Selectable reduced drive  
T
strength  
Available in 28-Pin 209mil SSOP (QSOP).  
FREQUENCY TABLES  
DESCRIPTION  
ASIC1 (MHz)  
PCI* (MHz)  
ASIC2  
(MHz)  
CPU  
CLK_SEL1  
CLK_SEL0  
ASIC1_SEL  
=1  
ASIC1_SEL  
=0  
PCI_SEL  
PCI_SEL  
=M  
(MHz)  
The PLL702-01 is a low cost, low jitter, and high  
=0  
performance clock synthesizer for generic PowerPC based  
applications. It provides one CPU clock, three ASIC  
outputs, one PCI output, and a selectable 48, 30 or 12MHz  
(USB) output. The user can choose between 9 different  
CPU clock frequencies, while the ASIC output can be  
identical or half of the CPU frequency. Low EMI Spread  
Spectrum Technology is available for the CPU, ASIC and  
PCI clocks. The CPU drive strength is user selectable from  
100% to 67%. All frequencies are generated from a single  
low cost 14.31818MHz crystal. The CPU and ASIC clock  
can be driven from an independent 2.5V power supply.  
0
0
0
M
1
50  
66  
50  
66  
25  
33  
50  
66  
62.5  
66.7  
31.25  
33.35  
31.25  
33.35  
33.35  
33.35  
33.35  
31.25  
32.75  
0
75  
75  
37.5  
40  
75  
62.5  
66.7  
66.7  
66.7  
66.7  
62.5  
65.5  
M
M
M
1
0
80  
80  
80  
M
1
83  
83  
41.5  
45  
83  
90  
90  
90  
0
100  
125  
133  
100  
125  
133  
50  
100  
125  
133  
1
M
1
62.5  
66.5  
1
Notes: When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When  
CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification.  
* PCI_SEL=1 sets the Tri-state (output disabled) mode of the output.  
BLOCK DIAGRAM  
Control  
Logic  
USB_SEL  
USB  
PLL  
CPU_CLK  
ASIC1  
PLL  
SST  
DIV 2  
XIN  
ASIC2(A:B)  
XTAL  
ASIC2_OE  
OSC  
XOUT  
PCI  
PCI_OE  
SSC(0:1)  
CLK_SEL(0:1)  
ASIC1_SEL  
PCI_SEL  
Control  
Logic  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/05 Page 1  

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