Datasheet > P5020NXN1TNB

P5020NXN1TNB

更新时间： 2024-11-07 14:59:23

品牌	Logo	应用领域
恩智浦 - NXP		PC 双倍数据速率
页数	文件大小	规格书
2页	123K
描述
QorIQ, 64-Bit Power Arch SoC, 2 X 1.8GHz, DDR3, PCIe, GbE, SRIO, HW Accel, -40 to 105C R2.0

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P5020NXN1TNB 数据手册

QorIQ Communications Platforms

P Series

QorIQ P5020 and P5010

communications processors

Overview

e5500 Core

DPAA Hardware Accelerators

The QorIQ P5 family delivers scalable 64-bit

processing with single-, dual- and quad-core

devices. With frequencies scaling up to

2.0 GHz, a tightly coupled cache hierarchy

for low latency and integrated hardware

acceleration, the P5020 (dual-core) and

P5010 (single-core) devices are ideally suited

for compute intensive, power-conscious

control plane applications.

The P5020 is based on the 64-bit e5500

Power Architecture^®core. The e5500

core uses a seven-stage pipeline for low

latency response to unpredictable code

execution paths, boosting its single-threaded

performance. Key features:

Frame manager (FMAN)

12 Gb/s classify, parse

and distribute

Buffer manager (BMAN)

Queue manager (QMAN) Up to 2²⁴queues

64 buffer pools

Security (SEC)

17 Gb/s: 3 DES, AES

10 Gb/s aggregate

Pattern matching engine

(PME)

RapidIO^®manager

Supports Type 9 and

Type 11 messaging

• Supports up to 2 GHz core frequencies

• Tightly coupled low latency cache

hierarchy: 32 KB I/D (L1), 512 KB L2

per core

RAID5/6 engine

Calculates parity for

network attached

storage and direct

attached storage

applications

Target Markets

and Applications

• Up to 2 MB of shared platform cache (L3)

• 3 DMIPS/MHz per core

The P5020 is designed for high-performance,

power-constrained control plane applications

and provides an ideal combination of core

performance, integrated accelerators and

advanced I/O required for the following

compute-intensive applications:

Data Path Acceleration

Architecture (DPAA)

The P5020 integrates QorIQ DPAA, an

innovative multicore infrastructure for

• Up to 64 GB of addressable memory space

• Hybrid 32-bit mode to support legacy

software and seamless transition to 64-bit

architecture

scheduling work to cores (physical and virtual),

hardware accelerators and network interfaces.

The FMAN, a primary element of the DPAA,

parses headers from incoming packets and

classifies and selects data buffers with optional

policing and congestion management. The

FMAN passes its work to the QMAN, which

assigns it to cores or accelerators with a multi-

level scheduling hierarchy. The P5020 also

offers accelerators for cryptography, enhanced

regular expression pattern matching and

RAID5/6 offload.

• Enterprise equipment: Router, switch,

services

Virtualization

The P5020 includes support for hardware-

assisted virtualization. The e5500 core offers

an extra core privilege level (hypervisor).

Virtualization software for the P5 family

includes kernel-based virtual machine (KVM),

Linux^®containers, Freescale hypervisor and

commercial virtualization software from Green

Hills^®Software and Enea^®.

• Data center: Server appliance, SAN

storage controller, iSCSI controller,

FCoE bridging

• Aerospace and defense

• Industrial computing: Single-board

computers, test/measurement, robotics

QorIQ P5020/P5010 Processors Block Diagram

*Only Available on P5020

1024 KB

Frontside CoreNet

Platform Cache

64-bit

Power Architecture^®

e5500 Core

DDR2/3

512 KB

Backside

L2 Cache

Memory Controller

1024 KB

Frontside CoreNet

Platform Cache

64-bit

DDR2/3

Memory Controller

32 KB

D Cache

32 KB

I Cache

Security Fuse Processor

2x Full Speed USB w/PHY

eSDHC

CoreNet Coherency Fabric

Peripheral Access

Management Unit

PAMU

eLBC

Frame Manager

Real-Time Debug

Serial

RapidIO^®

Mgr.

RapidIO

Message

Unit

SD/MMC

Queue

Mgr.

Security

4.0

Watchpoint

Cross

Trigger

2x DMA

Parse, Classify,

Distribute

2x DUART

2x I²C

SATA SATA

2.0

Perf.

Monitor

Pattern

Match

Engine

2.0

Trace

1GE 1GE

RAID

5/6

Engine

PCIe/

SPI, GPIO

Buffer

Mgr.

PCIe

SRIO

PCIe

10 GE

1GE

PCIe

Aurora

1GE 1GE

18-Lane 5 GHz SerDes

Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)

Accelerators and Memory Control Networking Elements

Basic Peripherals and Interconnect

中文翻译

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P5020NXN1TNB 替代型号

型号	品牌	替代类型	描述	数据表
P5020NXN7TNB	NXP	完全替代	QorIQ, 64-Bit Power Arch SoC, 2 X 1.8GHz, DDR3, PCIe, GbE, SRIO, HW Accel, -40 to 105C R2.

与P5020NXN1TNB相关器件

型号	品牌	获取价格	描述	数据表
P5020NXN1VNB	NXP	获取价格	IC MPU Q OR IQ 2.0GHZ 1295FCBGA
P5020NXN7QMB	NXP	获取价格	QorIQ, 64-Bit Power Arch SoC, 2 X 1.6GHz, DDR3, PCIe, GbE, SRIO, HW Accel, -40 to 105C R2.
P5020NXN7TNB	NXP	获取价格	QorIQ, 64-Bit Power Arch SoC, 2 X 1.8GHz, DDR3, PCIe, GbE, SRIO, HW Accel, -40 to 105C R2.
P5020NXN7VNB	NXP	获取价格	QorIQ, 64-Bit Power Arch SoC, 2 X 2.0GHz, DDR3, PCIe, GbE, SRIO, HW Accel, -40 to 105C R2.
P5021	NXP	获取价格	P5021 QorIQ Integrated Processor Data Sheet
P502-100	TRIPPLITE	获取价格	VGA Coaxial High-Resolution Monitor Cable with RGB Coaxial (HD15 M/M), 2048 x 1536 (1080p)
P5021NSE12QB	NXP	获取价格	QorIQ, 64-Bit Power Arch SoC, 2 X 2.2GHz, DDR3/3Lw/ECC, PCIe, 1/10GbE, SATA, SEC, 0 to 105
P5021NSE12QC	NXP	获取价格	RISC PROCESSOR
P5021NSE72QC	NXP	获取价格	QorIQ, 64-Bit Power Arch SoC, 2 X 2.2GHz, DDR3/3L w/ECC, PCIe, 1/10GbE, SATA, SEC, 0 to 90
P5021NSE7TMC	NXP	获取价格	QorIQ, 64-Bit Power Arch SoC, 2 X 1.8GHz, DDR3/3Lw/ECC, PCIe, 1/10GbE, SATA, SEC, 0 to 105

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