Datasheet > P4C163L-25LM

P4C163L-25LM

更新时间： 2024-11-30 23:25:19

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
8页	84K
描述
x9 SRAM

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中文翻译

获取价格

数据手册

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P4C163L-25LM 数据手册

P4C163/163L

P4C163/P4C163L

ULTRA HIGH SPEED 8K x 9

STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

Single 5V±10% Power Supply

High Speed (Equal Access and Cycle Times)

– 25/35ns (Commercial)

Data Retention with 2.0V Supply, 10 µA Typical

Current (P4C163L Military)

– 25/35/45ns (Military)

Common I/O

Low Power Operation (Commercial/Military)

– 690/800 mW Active – 25

– 193/220 mW Standby (TTL Input)

– 5.5 mW Standby (CMOS Input) P4C163L

Fully TTL Compatible Inputs and Outputs

Standard Pinout (JEDEC Approved)

– 28-Pin 300 mil DIP, SOJ

– 28-Pin 350 x 550 mil LCC

– 28-Pin CERPACK

Output Enable and Dual Chip Enable Control

Functions

DESCRIPTION

Access times as fast as 25 nanoseconds are available, per-

mitting greatly enhanced system operating speeds. CMOS

is used to reduce power consumption in both active and

standby modes.

The P4C163 and P4C163L are 73,728-bit ultra high-speed

static RAMs organized as 8K x 9. The CMOS memories re-

quire no clocks or refreshing and have equal access and

cycle times. Inputs are fully TTL-compatible. The RAMs op-

erate from a single 5V±10% tolerance power supply. With

battery backup, data integrity is maintained for supply volt-

agesdownto2.0V.Currentdrainis10µAfroma2.0Vsupply.

The P4C163 and P4C163L are available in 28-pin 300 mil

DIPandSOJand28-pin350x550milLCCpackagesprovid-

ing excellent board level densities.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

A₀

73,728-BIT

ROW

MEMORY

SELECT

ARRAY

A₇

I/O₁

INPUT

DATA

COLUMN I/O

CONTROL

I/O

I/O₉

CE1

I/O

14 15 16

I/O

COLUMN

SELECT

I/O

GND

A₈

A₁₂

DIP (P5, C5), SOJ (J5)

LCC (L5)

CERPACK (F4) SIMILAR

TOP VIEW

Means Quality, Service and Speed

1Q97

109

12 3 4 5 6 7 8

中文翻译

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