Datasheet > P4C1256-35CWI

P4C1256-35CWI

更新时间： 2024-11-19 07:37:59

品牌	Logo	应用领域
PYRAMID		静态存储器
页数	文件大小	规格书
16页	1155K
描述
Standard SRAM, 32KX8, 35ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, SIDE BRAZED, DIP-28

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中文翻译

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P4C1256-35CWI 数据手册

P4C1256

HIGH SPEED 32K x 8

STATIC CMOS RAM

FEATURES

High Speed (Equal Access and Cycle Times)

– 12/15/20/25/35 ns (Commercial)

– 15/20/25/35/45 ns (Industrial)

– 20/25/35/45/55/70 ns (Military)

Low Power

Single 5V±10% Power Supply

Easy Memory Expansion Using CE and OE Inputs

Common Data I/O

Fast t_OE

Automatic Power Down

Packages

– 28-Pin 300 mil DIP, SOJ, TSOP

– 28-Pin 300 mil Ceramic DIP

– 28-Pin 600 mil Plastic and Ceramic DIP

– 28-Pin CERPACK

– 28-Pin Solder Seal Flat Pack

– 28-Pin SOP

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

ꢀ Advanced CMOS Technology

– 28-Pin LCC (350 mil x 550 mil)

– 32-Pin LCC (450 mil x 550 mil)

DESCRIPTIOꢀ

The P4C1256 is a 262,144-bit high-speed CMOS static

RAM organized as 32K x 8. The CMOS memory requires

no clocks or refreshing, and has equal access and cycle

times. InputsarefullyTTL-compatible. TheRAMoperates

from a single 5V±10% tolerance power supply.

with matching access and cycle times. Memory locations

are speciﬁed on address pinsA₀toA₁₄. Reading is accom-

plished by device selection (CE) and output enabling (OE)

while write enable (WE) remains HIGH. By presenting the

address under these conditions, the data in the addressed

memorylocationispresentedonthedatainput/outputpins.

The input/output pins stay in the HIGH Z state when either

CE or OE is HIGH or WE is LOW.

Access times as fast as 12 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilized to

reduce power consumption to a low level. The P4C1256

is a member of a family of PACE RAM™ products offering

fast access times.

PackageoptionsfortheP4C1256include28-pinDIP,SOJ,

and TSOP packages. For military temperature range,

Ceramic DIP and LCC packages are available.

The P4C1256 devices provides asynchronous operation

FUꢀCTIOꢀAL BLOCK DIAꢁRAM

PIꢀ COꢀFIꢁURATIOꢀS

DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)

CERPACK (F4, FS-5) SIMILAR

LCC and TSOP conﬁgurations at end of datasheet

Document # SRAM119 REV I

Revised July 2010

12 3 4 5 6 7...16

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与P4C1256-35CWI相关器件

型号	品牌	获取价格	描述	数据表
P4C1256-35CWILF	PYRAMID	获取价格	Standard SRAM, 32KX8, 35ns, CMOS, CDIP28, 0.600 INCH, ROHS COMPLIANT, CERAMIC, SIDE BRAZED
P4C1256-35CWMB	PYRAMID	获取价格	Standard SRAM, 32KX8, 35ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, SIDE BRAZED, DIP-28
P4C1256-35CWMBLF	PYRAMID	获取价格	Standard SRAM, 32KX8, 35ns, CMOS, CDIP28, 0.600 INCH, ROHS COMPLIANT, CERAMIC, SIDE BRAZED
P4C1256-35DC	PYRAMID	获取价格	暂无描述
P4C1256-35DCLF	PYRAMID	获取价格	HIGH SPEED 32K x 8 STATIC CMOS RAM
P4C1256-35DILF	PYRAMID	获取价格	HIGH SPEED 32K x 8 STATIC CMOS RAM
P4C1256-35DM	PYRAMID	获取价格	Standard SRAM, 32KX8, 35ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28
P4C1256-35DMB	PYRAMID	获取价格	Standard SRAM, 32KX8, 35ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28
P4C1256-35DMBLF	PYRAMID	获取价格	HIGH SPEED 32K x 8 STATIC CMOS RAM
P4C1256-35DMLF	PYRAMID	获取价格	HIGH SPEED 32K x 8 STATIC CMOS RAM

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