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P4C1256-35FILF PDF预览

P4C1256-35FILF

更新时间: 2024-11-12 03:36:55
品牌 Logo 应用领域
PYRAMID /
页数 文件大小 规格书
17页 170K
描述
HIGH SPEED 32K x 8 STATIC CMOS RAM

P4C1256-35FILF 数据手册

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P4C1256  
HIGH SPEED 32K x 8  
STATIC CMOS RAM  
FEATURES  
Fully TTL Compatible Inputs and Outputs  
Advanced CMOS Technology  
Fast tOE  
Automatic Power Down  
Packages  
High Speed (Equal Access and Cycle Times)  
— 12/15/20/25/35 ns (Commercial)  
— 15/20/25/35/45 ns (Industrial)  
— 20/25/35/45/55/70 ns (Military)  
Low Power  
—28-Pin 300 mil DIP, SOJ, TSOP  
—28-Pin 300 mil Ceramic DIP  
—28-Pin 600 mil Ceramic DIP  
—28-Pin CERPACK  
—28-Pin SOP  
—28-Pin LCC (350 mil x 550 mil)  
—32-Pin LCC (450 mil x 550 mil)  
Single 5V±10% Power Supply  
Easy Memory Expansion Using CE and OE  
Inputs  
Common Data I/O  
Three-State Outputs  
DESCRIPTION  
The P4C1256 device provides asynchronous operation  
with matching access and cycle times. Memory loca-  
tions are specified on address pins A0 to A14. Reading  
is accomplished by device selection (CE and output  
enabling (OE) while write enable (WE) remains HIGH.  
By presenting the address under these conditions, the  
data in the addressed memory location is presented on  
the data input/output pins. The input/output pins stay  
in the HIGH Z state when either CE or OE is HIGH or  
WE is LOW.  
The P4C1256 is a 262,144-bit high-speed CMOS  
static RAM organized as 32Kx8. The CMOS memory  
requires no clocks or refreshing, and has equal access  
and cycle times. Inputs are fully TTL-compatible. The  
RAM operates from a single 5V±10% tolerance power  
supply.  
Access times as fast as 12 nanoseconds permit greatly  
enhanced system operating speeds. CMOS is utilized  
to reduce power consumption to a low level. The  
P4C1256 is a member of a family of PACE RAM™ prod-  
ucts offering fast access times.  
Package options for the P4C1256 include 28-pin 300  
mil DIP, SOJ and TSOP packages. For military tempera-  
ture range, Ceramic DIP and LCC packages are avail-  
able.  
PIN CONFIGURATIONS  
FUNCTIONAL BLOCK DIAGRAM  
DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)  
CERPACK (F4) SIMILAR  
See end of datasheet for LCC and TSOP  
pin configurations.  
Document # SRAM119 REV G  
Revised June 2007  
1

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