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P1757M-30PGMB

更新时间： 2024-09-20 13:12:03
品牌 Logo 应用领域
PYRAMID /
页数 文件大小 规格书
34页 651K
描述
Microprocessor, 30MHz, CMOS, CPGA144, PGA-144

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P1757M-30PGMB 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：PGA
包装说明：PGA,针数：144
Reach Compliance Code：compliantECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01风险等级：5.78
地址总线宽度：16边界扫描：NO
最大时钟频率：30 MHz外部数据总线宽度：16
格式：FIXED POINT集成缓存：NO
JESD-30 代码：S-CPGA-P144低功率模式：YES
端子数量：144最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：PGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified速度：30 MHz
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：PIN/PEG端子位置：PERPENDICULAR
处于峰值回流温度下的最长时间：NOT SPECIFIEDuPs/uCs/外围集成电路类型：MICROPROCESSOR
Base Number Matches：1

P1757M-30PGMB 数据手册

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PACE1757M/ME  
COMPLETE EMBEDDED CPU SUBSYSTEM  
FEATURES  
Programmable memory and I/O data wait  
state generation permits up to four different  
memory speeds in the same system.  
Implements complete MIL-STD-1750A ISA including  
optional MMU, MFSR, and BPU functions.  
Two throughput options:  
P1757M 2.5MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz  
P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz  
Programmable address wait states.  
Sixteen levels of interrupts are provided per  
MIL-STD-1750A. Interrupts can be either  
edge- or level-sensitive.  
All MIL-STD-1750A data formats and address  
types implemented.  
Fault detection and handling  
P1757ME includes additional matrix and vector  
instructions to enhance throughput in  
navigation, DSP transcendental and other  
complex alorithms.  
Programmable detection of unimplemented  
memory or illegal I/O addresses.  
Full implementation of MIL-STD-1750A fault  
register.  
Error detection and correction and parity bit  
provided.  
External address error detection.  
Testability and diagnostics.  
Separate high drive external address & data  
busses.  
First falling address and data registers.  
10MHz data rate at 40MHz CPU clock  
System support functions included:  
Built in test - runs automatically at power on  
and after each reset. All hardware blocks  
and external busses examined. Hardware  
pass/fail for catastrophic failures. Status  
register indicates failed test.  
Arbitrator for use in tightly coupled  
multiprocessor design. Bus control provided  
to aid in implementation of multi-processor  
systems.  
Console operating mode which allows  
operator to examine and change contents of  
registers within the CPU, any system  
memory location, or the I/O subsystems.  
MIL-STD-1750A timers A & B, programmable  
watch dog timer and programmable bus time-  
out function.  
Single 144-pin Quad straight lead or Gullwing  
1.5 square inches of board surface.  
Start up ROM support per MIL-STD-1750A.  
DMA support for logical and physical memory  
addresses.  
Operating temperature range -55 to +125°C;  
single 5V ± 10% V power supply; power  
CC  
dissipation < 1.9W (worst case at 40 MHz).  
GENERAL DESCRIPTION  
The PACE 1757M uses the application-proven PACE  
1750A microprocessor, the PACE 1753, and the PACE  
1754. The PACE1757ME uses the enhanced PACE  
1750AEmicroprocessor,whichhasadditionalinstructions  
thatprovidehighthroughputfortranscendentalfunctions,  
navigational algorithms, and DSP functions. The PACE  
1750AE is an architectural enhancement of the PACE  
1750A.  
All functions required for a complete MIL-STD-1750A  
embedded CPU subsystem are in this single VLSI  
microcircuit occupying 1.5 square inches of board space  
with less than 1.9 watts of power dissipation at 40 MHz.  
Pyramid'sP1757M/MEisacomplete,singlepackage,3.6  
MIPS subsystem solution to embedded processor  
requirements.  
Do c um e nt # MICRO-10 REV B  
Re vise d Aug ust 2005  
1234567...34

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