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P16C2308-1LI PDF预览

P16C2308-1LI

更新时间: 2024-09-15 23:25:03
品牌 Logo 应用领域
其他 - ETC 时钟驱动器输出元件
页数 文件大小 规格书
9页 441K
描述
EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|TSSOP|16PIN|PLASTIC

P16C2308-1LI 数据手册

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PI6C2308  
Zero-Delay Clock Buffer  
ProductFeatures  
FunctionalDescription  
Maximumratedfrequency:133MHz  
Lowcycle-to-cyclejitter  
The PI6C2308 is a PLL-based, zero-delay buffer, with the ability  
to distribute eight outputs of up to 133 MHz at 3.3 V. Two banks of  
four outputs exist, and, depending on product option ordered, can  
supply either reference frequency, prescaled half frequency, or  
multiplied2xor4xinputclockfrequencies. ThePI6C2308familyhas  
a power-sparing feature: when input SEL2 is 0, the component will  
3-state one or both banks of outputs depending on the state of input  
SEL1. A PLL bypass test mode also exists. This product line is  
available in high-drive and industrial environment versions.  
Input to output delay, less than 200ps  
External feedback pin allows outputs to be synchronized  
to the clock input  
5V tolerant input*  
Operatesat3.3VVDD  
Test mode allows bypass of the PLL for system testing  
purposes (e.g., IBIS measurements)  
An external feedback pin is used to synchronize the outputs to the  
input; the relationship between loading of this signal and the other  
outputs determines the input-output delay.  
Clock frequency multipliers ½x to 4x dependent on option  
Space-saving Packages:  
16-pin,150-milSOIC (W)  
16-pin173-milTSSOP (L)  
The PI6C2308 is characterized for both commercial and industrial  
operation.  
* FB_IN and CLKIN must reference the same voltage thresh-  
olds for the PLL to deliver zero delay skewing  
Notice: This device is subject to import restriction. Please refer  
to the Import Restriction Notice under the Ordering Information  
section.  
BlockDiagram  
PinConfigurationPI6C2308  
FB_IN  
CLKIN  
÷2  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
OUTA1  
OUTA2  
16  
15 OUTA4  
1
2
3
4
5
6
7
8
FB_IN  
Option (-3, -4)  
14  
13  
12  
11  
10  
9
OUTA3  
16-Pin  
W,L  
SEL1  
SEL2  
Decode  
Logic  
V
V
GND  
DD  
DD  
GND  
OUTB1  
OUTB2  
SEL2  
÷2  
OUTB4  
OUTB3  
SEL1  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
Option (-2, -3)  
PI6C2308 (-1, -1H, -2, -3, -4)  
FB_IN  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
SEL2  
SEL1  
Decode  
Logic  
÷2  
MUX  
PI6C2308-6  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
PS8384D  
12/07/01  
1

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