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OMAPL138BZCED4 PDF预览

OMAPL138BZCED4

更新时间： 2024-01-15 20:20:40
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德州仪器 - TI /
页数 文件大小 规格书
287页 1875K
描述
OMAP-L138 C6-Integra DSP+ARM Processor

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OMAPL138BZCED4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA, BGA361,19X19,25针数：361
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.82
地址总线宽度：桶式移位器：NO
边界扫描：YES最大时钟频率：50 MHz
外部数据总线宽度：格式：FLOATING POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B361
JESD-609代码：e1长度：13 mm
低功率模式：YES湿度敏感等级：3
端子数量：361封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA361,19X19,25
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.2,1.8/3.3 V
认证状态：Not Qualified座面最大高度：1.3 mm
子类别：Other uPs/uCs/Peripheral ICs最大供电电压：1.35 V
最小供电电压：0.95 V标称供电电压：1 V
表面贴装：YES技术：CMOS
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.65 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

OMAPL138BZCED4 数据手册

 浏览型号OMAPL138BZCED4的Datasheet PDF文件第2页浏览型号OMAPL138BZCED4的Datasheet PDF文件第3页浏览型号OMAPL138BZCED4的Datasheet PDF文件第4页浏览型号OMAPL138BZCED4的Datasheet PDF文件第5页浏览型号OMAPL138BZCED4的Datasheet PDF文件第6页浏览型号OMAPL138BZCED4的Datasheet PDF文件第7页 
OMAP-L138  
www.ti.com  
SPRS586C–JUNE 2009–REVISED MAY 2011  
OMAP-L138 C6-Integra™ DSP+ARM® Processor  
Check for Samples: OMAP-L138  
1 OMAP-L138 C6-Integra™ DSP+ARM® Processor  
1.1 Features  
12  
– Normalization, Saturation, Bit-Counting  
• Highlights  
– Compact 16-Bit Instructions  
– Dual Core SoC  
• C674x Two Level Cache Memory Architecture  
– 32K-Byte L1P Program RAM/Cache  
– 32K-Byte L1D Data RAM/Cache  
•
•
375/456-MHz ARM926EJ-S™ RISC MPU  
375/456-MHz C674x Fixed/Floating-Point  
VLIW DSP  
– Enhanced Direct-Memory-Access Controller  
– 256K-Byte L2 Unified Mapped RAM/Cache  
– Flexible RAM/Cache Partition (L1 and L2)  
(EDMA3)  
– Serial ATA (SATA) Controller  
• Enhanced Direct-Memory-Access Controller 3  
– DDR2/Mobile DDR Memory Controller  
(EDMA3):  
– Two Multimedia Card (MMC)/Secure Digital  
– 2 Channel Controllers  
(SD) Card Interface  
– 3 Transfer Controllers  
– LCD Controller  
– Video Port Interface (VPIF)  
– 64 Independent DMA Channels  
– 16 Quick DMA Channels  
– 10/100 Mb/s Ethernet MAC (EMAC)  
– Programmable Real-Time Unit Subsystem  
– Three Configurable UART Modules  
– USB 1.1 OHCI (Host) With Integrated PHY  
– USB 2.0 OTG Port With Integrated PHY  
– One Multichannel Audio Serial Port  
– Two Multichannel Buffered Serial Ports  
• Dual Core SoC  
– 375/456-MHz ARM926EJ-S™ RISC MPU  
– 375/456-MHz C674x Fixed/Floating-Point  
VLIW DSP  
• ARM926EJ-S Core  
– Programmable Transfer Burst Size  
• TMS320C674x Floating-Point VLIW DSP Core  
– Load-Store Architecture With Non-Aligned  
Support  
– 64 General-Purpose Registers (32 Bit)  
– Six ALU (32-/40-Bit) Functional Units  
•
Supports 32-Bit Integer, SP (IEEE Single  
Precision/32-Bit) and DP (IEEE Double  
Precision/64-Bit) Floating Point  
•
•
Supports up to Four SP Additions Per  
Clock, Four DP Additions Every 2 Clocks  
Supports up to Two Floating Point (SP or  
DP) Reciprocal Approximation (RCPxP)  
and Square-Root Reciprocal  
– 32-Bit and 16-Bit (Thumb®) Instructions  
– DSP Instruction Extensions  
– Single Cycle MAC  
Approximation (RSQRxP) Operations Per  
Cycle  
– ARM® Jazelle® Technology  
– EmbeddedICE-RT™ for Real-Time Debug  
• ARM9 Memory Architecture  
– 16K-Byte Instruction Cache  
– 16K-Byte Data Cache  
– Two Multiply Functional Units  
•
Mixed-Precision IEEE Floating Point  
Multiply Supported up to:  
–
–
–
–
2 SP x SP → SP Per Clock  
2 SP x SP → DP Every Two Clocks  
2 SP x DP → DP Every Three Clocks  
2 DP x DP → DP Every Four Clocks  
– 8K-Byte RAM (Vector Table)  
– 64K-Byte ROM  
• C674x™ Instruction Set Features  
– Superset of the C67x+™ and C64x+™ ISAs  
– Up to 3648/2746 C674x MIPS/MFLOPS  
– Byte-Addressable (8-/16-/32-/64-Bit Data)  
– 8-Bit Overflow Protection  
•
Fixed Point Multiply Supports Two 32 x  
32-Bit Multiplies, Four 16 x 16-Bit  
Multiplies, or Eight 8 x 8-Bit Multiplies per  
Clock Cycle, and Complex Multiples  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
– Hardware Support for Modulo Loop  
– Bit-Field Extract, Set, Clear  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2011, Texas Instruments Incorporated  
 
 
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OMAPL138BZCED4 替代型号

型号 品牌 替代类型 描述 数据表
OMAPL138EZCED4 TI

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