PRELIMINARY
April 1991
NS32381-15/NS32381-20/NS32381-25/NS32381-30
Floating-Point Unit
General Description
The NS32381 is a second generation, CMOS, floating-point
slave processor that is fully software compatible with its
forerunner, the NS32081 FPU. The NS32381 FPU functions
The FPU is fabricated with National’s advanced double-met-
al CMOS process.
with all Series 32000 and Series 32000/EP CPUs in a
É
Features
Y
tightly coupled slave configuration. The performance of the
NS32381 has been increased over the NS32081 by archi-
tecture improvements, hardware enhancements, and higher
clock frequencies. Key improvements include the addition of
a 32-bit slave protocol, an early done algorithm to increase
CPU/FPU parallelism, an expanded register set, an auto-
matic power down feature, expanded math hardware, and
additional instructions.
Compatible with all Series 32000 and Series 32000/EP
CPUs
Y
Selectable 16-bit or 32-bit Slave Protocol
Y
Compatible with IEEE Standard 754-1985 for binary
floating point arithmetic
Y
Early done algorithm
Y
Single (32-bit) and double (64-bit) precision operations
Y
Eight on-chip (64-bit) data registers
The NS32381 FPU contains eight 64-bit data registers and
a Floating-Point Status Register (FSR). The FPU executes
20 instructions, and operates on both single and double-
precision operands. Three separate processors in the
NS32381 manipulate the mantissa, sign, and exponent.
Y
Automatic power down mode
Y
Full upward compatibility with existing 32000 software
Y
High speed double-metal CMOS design
Y
68-pin PGA package
Y
The CPU and NS32381 FPU form a tightly coupled comput-
er cluster, which appears to the user as a single processing
unit. The CPU and FPU communication is handled automati-
cally, and is user transparent.
68-pin plastic package
FPU Block Diagram
TL/EE/9157–1
FIGURE 1-1
Series 32000É and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/EE/9157
RRD-B30M115/Printed in U. S. A.