Functional Description
DEVICE OPERATION
This assures that all deselected memory devices are in their
low power standby modes and that the output pins are ac-
tive only when data is desired from a particular memory de-
vice.
The six modes of operation of the EPROM are listed in Ta-
ble I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are V
CC
and
OE/V . The OE/V power supply must be at 12.75V dur-
PP PP
ing the three programming modes, and must be at 5V in the
Programming
CAUTION: Exceeding 14V on pin 22 (OE/V ) will damage
PP
the EPROM.
other three modes. The V power supply must be at 6.25V
CC
during the three programming modes, and at 5V in the other
three modes.
Initially, and after each erasure, all bits of the EPROM are in
the ‘‘1’s’’ state. Data is introduced by selectively program-
ming ‘‘0’s’’ into the desired bit locations. Although only
‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be pre-
sented in the data word. The only way to change a ‘‘0’’ to a
‘‘1’’ is by ultraviolet light erasure.
Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE/PGM) is the power control and should be
The EPROM is in the programming mode when the OE/V
PP
used for device selection. Output Enable (OE/V ) is the
PP
is at 12.75V. It is required that at least a 0.1 mF capacitor be
output control and should be used to gate data to the output
pins, independent of device selection. Assuming that ad-
placed across V
CC
to ground to suppress spurious voltage
transients which may damage the device. The data to be
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.
dresses are stable, address access time (t
) is equal to
ACC
the delay from CE to output (t ). Data is available at the
CE
outputs t
after the falling edge of OE, assuming that CE
OE
has been low and addresses have been stable for at least
–t
t
.
ACC OE
When the address and data are stable, an active low, TTL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be pro-
grammed.
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 385 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE/PGM input. When in standby
mode, the outputs are in a high impedance state, indepen-
dent of the OE input.
The EPROM is programmed with the Fast Programming Al-
gorithm shown in Figure 1. Each Address is programmed
with a series of 100 ms pulses until it verifies good, up to a
maximum of 25 pulses. Most memory cells will program with
a single 100 ms pulse.
Output Disable
The EPROM must not be programmed with a DC signal ap-
plied to the CE/PGM input.
The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all cir-
cuitry is enabled, except the outputs are in a high imped-
ance state (TRI-STATE).
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the parallel
EPROM may be connected together when they are pro-
grammed with the same data. A low level TTL pulse applied
to the CE/PGM input programs the paralleled EPROM.
Output OR-Typing
Because the EPROM is usually used in larger memory ar-
rays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM all
a) the lowest possible memory power dissipation, and
like inputs (including OE/V ) of the parallel EPROMs may
PP
be common. A TTL low level program pulse applied to an
b) complete assurance that output bus contention will not
occur.
EPROM’s CE/PGM input with OE/V at 12.75V will pro-
PP
gram that EPROM. A TTL high level CE/PGM input inhibits
the other EPROMs from being programmed.
To most efficiently use these two control lines, it is recom-
mended that CE/PGM be decoded and used as the primary
device selecting function, while OE/V
be made a com-
PP
mon connection to all devices in the array and connected to
the READ line from the system control bus.
7
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
