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NM27P512V120 PDF预览

NM27P512V120

更新时间: 2024-01-02 16:31:57
品牌 Logo 应用领域
美国国家半导体 - NSC 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
12页 178K
描述
524,288-Bit (64K x 8) Processor Oriented CMOS EPROM

NM27P512V120 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:120 ns
I/O 类型:COMMONJESD-30 代码:R-PQCC-J32
JESD-609代码:e0长度:13.995 mm
内存密度:524288 bit内存集成电路类型:OTP ROM
内存宽度:8功能数量:1
端子数量:32字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC32,.5X.6封装形状:RECTANGULAR
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:3.56 mm
最大待机电流:0.0001 A子类别:OTP ROMs
最大压摆率:0.04 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11.455 mmBase Number Matches:1

NM27P512V120 数据手册

 浏览型号NM27P512V120的Datasheet PDF文件第2页浏览型号NM27P512V120的Datasheet PDF文件第3页浏览型号NM27P512V120的Datasheet PDF文件第4页浏览型号NM27P512V120的Datasheet PDF文件第5页浏览型号NM27P512V120的Datasheet PDF文件第6页浏览型号NM27P512V120的Datasheet PDF文件第7页 
December 1993  
NM27P512  
524,288-Bit (64K x 8) Processor Oriented  
CMOS EPROM  
General Description  
Features  
Y
Fast output turn off to eliminate wait states  
Extended data hold time for microprocessor  
compatibility  
The NM27P512 is a 512K Processor Oriented EPROM con-  
figured as 64k x 8. It’s designed to simplify microprocessor  
interfacing while remaining compatible with standard  
EPROMs. It can reduce both wait states and glue logic  
when the specification improvements are taken advantage  
of in the system design. The NM27P512 is implemented in  
National’s advanced CMOS EPROM process to provide ex-  
cellent reliability and access times as fast as 120 ns.  
Y
Y
High performance CMOS  
Ð 120 ns access time  
Y
Y
JEDEC standard pin configuration  
Manufacturer’s identification code  
The interface improvements address two areas to eliminate  
the need for additional devices to adapt the EPROM to the  
microprocessor and to eliminate wait states at the termina-  
tion of the access cycle. Even with these improvements, the  
NM27P512 remains compatible with industry standard  
JEDEC pinout EPROMs. The maximum specification for out-  
put turn-off time has been reduced, eliminating the need for  
wait states at the end of a read cycle. Also, the minimum  
specification for output hold time has been increased, elimi-  
nating the need for external circuitry to hold the data.  
Block Diagram  
TL/D/11365–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
NSC800TM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/D/11365  
RRD-B30M105/Printed in U. S. A.  

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