Fairchild
Application Note 794
Using an EEPROM—
IIC Interface
NM24C02/03/04/05/08/09/
16/17
ration used by the IIC interface compared to that of the
MICROWIRE™ and SPI interface, reduced board space and pin
count allows the designer to have more creative flexibility while
reducing interconnecting cost.
INTRODUCTION
Fairchild Semiconductor’s NM24C EEPROMs are designed to
interface with Inter-Integrated Circuit (IIC) buses and hardware.
Fairchild’s electrically erasable programmable read only memo-
ries (EEPROMs) offer valuable security features (write protec-
tion), two write modes, three read modes and a wide variety of
memory sizes. Applications for the IIC bus and NM24C memories
are included in SANs (small-area networks), stereos, televisions,
automobiles and other scaled-down systems that don’t require
tremendous speeds but instead cost efficiency and design sim-
plicity.
OPERATING Fairchild SEMICONDUCTOR’S
NM24Cs
TheNM24CE2PROMsrequireonlysixsimpleoperatingcodesfor
transmittingorreceivingbitsofinformationoverthe2-wireIICbus.
These fields are explained in greater detail below and briefly
described hereafter: a start bit, a 7-bit slave address, a read/write
bit which defines whether the slave is a transmitter or receiver, an
acknowledge bit, message bits divided into 8-bit segments and a
stop bit.
IIC BACKGROUND
The IIC bus configuration is an amalgam of microcontrollers and
peripheral controllers. By definition: a device that transmits sig-
nalsontotheIICbusisthe“transmitter”andadevicethatreceives
signals is the “receiver”; a device that controls signal transfers on
thelineinadditiontocontrollingtheclockfrequencyisthe“master”
and a device that is controlled by the master is the “slave”. The
master can transmit or receive signals to or from a slave, respec-
tively, or control signal transfers between two slaves, where one
is the transmitter and the other is the receiver. It is possible to
combineseveralmasters,inadditiontoseveralslaves,ontoanIIC
bus to form a multimaster system. If more than one master
simultaneously tries to control the line, an arbitration procedure
decides which master gets priority. The maximum number of
devices connected to the bus is dictated by the maximum allow-
able capacitance on the lines, 400 pF, and the protocol’s address-
ing limit of 16k; typical device capacitance is 10 pF. Up to eight
E2PROMs can be connected to an IIC bus, depending on the size
of the memory device implemented.
For efficient and faster serial communication between devices,
the NM24C Family features page write and sequential read.
TheNM24C03/C05/C09/C16/C17Familyoffersasecurityfeature
in addition to standard features found in the NM24C02/C04/C08/
C16Family. Thesecurityfeatureisbeneficial inthatitallowsRead
Only Memory (ROM) to be implemented in the upper half of the
memory to prevent any future programming in that particular chip
section; the remaining memory that has not been write protected
can still be programmed. The security feature in the NM24C03/
C05/C09/C17 Family does not require immediate implementation
when the device is interfaced to the IIC bus, which gives the
designer the option to choose this feature at a later date. Table 1
displays the following parameters: memory content, write protect
and the maximum number of individual IIC E2PROMs allowed on
anIICbusatonetimeifthetotallinecapacitanceiskeptbelow400
pF.
CodeusedtointerfacetheNM24CswithFairchildSemiconductor’s
COP8™ Microcontroller Family is listed in a latter section of this
application note for further information to the reader.
Simplicity of the IIC system is primarily due to the bidirectional 2-
wire design, a serial data line (SDA) and serial clock line (SKL),
and to the protocol format. Because of the efficient 2-wire configu-
TABLE 1.
Number of
Part No.
Write Protect
Max.
256x8 Page Blocks
Feature
No
Parts
NM24C02
NM24C03
NM24C04
NM24C05
NM24C08
NM24C09
NM24C16
NM24C17
1
1
2
2
4
4
8
8
8
8
4
4
2
2
1
1
Yes
No
Yes
No
Yes
No
Yes
1
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www.fairchildsemi.com