MC74VHC1GT04
Inverting Buffer /
CMOS Logic Level Shifter
LSTTL−Compatible Inputs
The MC74VHC1GT04 is a single gate inverting buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
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MARKING
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT04 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT04 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection
DIAGRAMS
5
SC−88A
DF SUFFIX
CASE 419A
5
VK M G
G
1
1
5
TSOP−5
DT SUFFIX
CASE 483
5
VK M G
G
1
1
when V = 0 V. These input and output structures help prevent
CC
device destruction caused by supply voltage − input/output voltage
mismatch, battery backup, hot insertion, etc.
VK = Device Code
M
G
= Date Code*
= Pb−Free Package
Features
• High Speed: t = 3.8 ns (Typ) at V = 5 V
PD
CC
(Note: Microdot may be in either location)
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
*Date Code orientation and/or position may vary
depending upon manufacturing location.
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V
IL
IH
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @ Load
OH
CC OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 105; Equivalent Gates = 26
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
PIN ASSIGNMENT
1
2
3
4
5
NC
IN A
GND
OUT Y
V
CC
• These Devices are Pb−Free and are RoHS Compliant
FUNCTION TABLE
A Input
Y Output
NC
IN A
GND
1
2
3
5
V
CC
L
H
L
H
4
OUT Y
ORDERING INFORMATION
Figure 1. Pinout (Top View)
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1
IN A
OUT Y
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
February, 2013 − Rev. 16
MC74VHC1GT04/D