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NLVVHC1GT08DFT2G PDF预览

NLVVHC1GT08DFT2G

更新时间: 2024-11-25 01:11:59
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
6页 122K
描述
2-Input AND Gate/CMOS Logic Level Shifter

NLVVHC1GT08DFT2G 数据手册

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MC74VHC1GT08  
2-Input AND Gate/CMOS  
Logic Level Shifter  
The MC74VHC1GT08 is an advanced high speed CMOS 2input  
AND gate fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
http://onsemi.com  
MARKING  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTLtype input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logiclevel translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the highvoltage power supply.  
The MC74VHC1GT08 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT08 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection when  
DIAGRAMS  
5
5
1
SC88A / SOT353 / SC70  
DF SUFFIX  
VT M G  
G
CASE 419A  
1
5
5
V
= 0 V. These input and output structures help prevent device  
CC  
VT M G  
1
TSOP5 / SOT23 / SC59  
DT SUFFIX  
G
destruction caused by supply voltage input/output voltage mismatch,  
battery backup, hot insertion, etc.  
1
Features  
CASE 483  
High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
VT = Device Code  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
M
G
= Date Code*  
= PbFree Package  
TTLCompatible Inputs: V = 0.8 V; V = 2 V  
IL  
IH  
CMOSCompatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
OH  
CC  
OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 64; Equivalent Gates = 15  
PIN ASSIGNMENT  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
These Devices are PbFree and are RoHS Compliant  
1
2
3
4
5
IN B  
IN A  
GND  
OUT Y  
V
CC  
5
4
IN B  
IN A  
GND  
V
CC  
1
2
3
FUNCTION TABLE  
Inputs  
Output  
Y
A
B
L
L
L
H
L
L
L
OUT Y  
H
H
L
H
H
Figure 1. Pinout (Top View)  
IN A  
IN B  
&
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
January, 2013 Rev. 12  
MC74VHC1GT08/D  

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