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NLVVHC1GT08DTT1G PDF预览

NLVVHC1GT08DTT1G

更新时间： 2024-11-10 01:11:59
品牌 Logo 应用领域
安森美 - ONSEMI 栅光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 122K
描述
2-Input AND Gate/CMOS Logic Level Shifter

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中文翻译

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NLVVHC1GT08DTT1G 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：TSOP包装说明：TSOP-5
针数：5Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：9 weeks
风险等级：1.41系列：AHC/VHC
JESD-30 代码：R-PDSO-G5JESD-609代码：e3
长度：3 mm负载电容（CL）：50 pF
逻辑集成电路类型：AND GATE最大I（ol）：0.008 A
湿度敏感等级：1功能数量：1
输入次数：2端子数量：5
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSOP
封装等效代码：TSOP5/6,.11,37封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3/5 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：11 ns
传播延迟（tpd）：16.5 ns认证状态：Not Qualified
施密特触发器：NO筛选级别：AEC-Q100
座面最大高度：1.1 mm子类别：Gates
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：0.95 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.5 mm
Base Number Matches：1

NLVVHC1GT08DTT1G 数据手册

 浏览型号NLVVHC1GT08DTT1G的Datasheet PDF文件第2页浏览型号NLVVHC1GT08DTT1G的Datasheet PDF文件第3页浏览型号NLVVHC1GT08DTT1G的Datasheet PDF文件第4页浏览型号NLVVHC1GT08DTT1G的Datasheet PDF文件第5页浏览型号NLVVHC1GT08DTT1G的Datasheet PDF文件第6页 
MC74VHC1GT08  
2-Input AND Gate/CMOS  
Logic Level Shifter  
The MC74VHC1GT08 is an advanced high speed CMOS 2−input  
AND gate fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
http://onsemi.com  
MARKING  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT08 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT08 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection when  
DIAGRAMS  
5
5
1
SC−88A / SOT−353 / SC−70  
DF SUFFIX  
VT M G  
G
CASE 419A  
1
5
5
V
= 0 V. These input and output structures help prevent device  
CC  
VT M G  
1
TSOP−5 / SOT−23 / SC−59  
DT SUFFIX  
G
destruction caused by supply voltage − input/output voltage mismatch,  
battery backup, hot insertion, etc.  
1
Features  
CASE 483  
• High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
VT = Device Code  
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
M
G
= Date Code*  
= Pb−Free Package  
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V  
IL  
IH  
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
OH  
CC  
OL  
CC  
• Power Down Protection Provided on Inputs and Outputs  
• Balanced Propagation Delays  
• Pin and Function Compatible with Other Standard Logic Families  
• Chip Complexity: FETs = 64; Equivalent Gates = 15  
PIN ASSIGNMENT  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
• These Devices are Pb−Free and are RoHS Compliant  
1
2
3
4
5
IN B  
IN A  
GND  
OUT Y  
V
CC  
5
4
IN B  
IN A  
GND  
V
CC  
1
2
3
FUNCTION TABLE  
Inputs  
Output  
Y
A
B
L
L
L
H
L
L
L
OUT Y  
H
H
L
H
H
Figure 1. Pinout (Top View)  
IN A  
IN B  
&
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
January, 2013 − Rev. 12  
MC74VHC1GT08/D  
123456

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