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NLVVHC1GT125DF1G PDF预览

NLVVHC1GT125DF1G

更新时间： 2024-11-25 01:08:55
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 138K
描述
Noninverting Buffer / CMOS Logic Level Shifter

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中文翻译

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NLVVHC1GT125DF1G 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：SOT-353包装说明：SC-70, SC-88A, SOT-353, 5 PIN
针数：5Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.37控制类型：ENABLE LOW
系列：AHC/VHCJESD-30 代码：R-PDSO-G5
JESD-609代码：e3长度：2 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.008 A湿度敏感等级：1
位数：1功能数量：1
端口数量：2端子数量：5
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP5/6,.08封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3/5 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：10.5 ns
传播延迟（tpd）：16 ns认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：1.1 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1.25 mmBase Number Matches：1

NLVVHC1GT125DF1G 数据手册

 浏览型号NLVVHC1GT125DF1G的Datasheet PDF文件第2页浏览型号NLVVHC1GT125DF1G的Datasheet PDF文件第3页浏览型号NLVVHC1GT125DF1G的Datasheet PDF文件第4页浏览型号NLVVHC1GT125DF1G的Datasheet PDF文件第5页浏览型号NLVVHC1GT125DF1G的Datasheet PDF文件第6页 
MC74VHC1GT125  
Noninverting Buffer /  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
The MC74VHC1GT125 is a single gate noninverting buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
http://onsemi.com  
MARKING  
The MC74VHC1GT125 requires the 3−state control input (OE) to  
be set High to place the output into the high impedance state.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT125 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT125 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection when  
DIAGRAMS  
5
5
1
W1 M G  
SC−88A / SOT−353 / SC−70  
DF SUFFIX  
G
1
5
CASE 419A  
5
W1 M G  
1
TSOP−5 / SOT−23 / SC−59  
DT SUFFIX  
G
1
V
CC  
= 0 V. These input and output structures help prevent device  
destruction caused by supply voltage − input/output voltage mismatch,  
battery backup, hot insertion, etc.  
CASE 483  
Features  
W1  
M
G
= Device Code  
= Date Code*  
= Pb−Free Package  
• High Speed: t = 3.5 ns (Typ) at V = 5 V  
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V  
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
PD  
CC  
CC  
A
(Note: Microdot may be in either location)  
IL  
IH  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
OH  
CC OL  
CC  
• Power Down Protection Provided on Inputs and Outputs  
• Balanced Propagation Delays  
• Pin and Function Compatible with Other Standard Logic Families  
• Chip Complexity: FETs = 62; Equivalent Gates = 16  
• These Devices are Pb−Free and are RoHS Compliant  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
PIN ASSIGNMENT  
1
2
3
4
5
OE  
IN A  
GND  
OUT Y  
V
CC  
OE  
IN A  
GND  
V
CC  
5
4
1
2
FUNCTION TABLE  
OE Input  
A Input  
Y Output  
OUT Y  
L
H
X
L
L
L
H
Z
3
H
Figure 1. Pinout (Top View)  
OE  
IN A  
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
September, 2012 − Rev. 14  
MC74VHC1GT125/D  
123456

中文翻译

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NLVVHC1GT125DF1G 替代型号

型号 品牌 替代类型 描述 数据表
NLVVHC1GT126DT1G ONSEMI

完全替代

 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL.Compatible Inputs
NLVVHC1GT126DF1G ONSEMI

完全替代

 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL.Compatible Inputs
NLVVHC1GT125DF2G ONSEMI

完全替代

 Noninverting Buffer / CMOS Logic Level Shifter

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