Datasheet > 微控制器和处理器 > 并行 IO 端口> NLVPCA9535EMTTXG

NLVPCA9535EMTTXG

更新时间： 2024-11-25 11:01:43

品牌	Logo	应用领域
安森美 - ONSEMI		控制器微控制器微控制器和处理器并行IO端口
页数	文件大小	规格书
20页	210K
描述
I/O 端口扩展器，I2C，16 位，低功耗带中断

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NLVPCA9535EMTTXG 数据手册

PCA9535E, PCA9535EC

16-bit Low-Power I/O

Expander for I²C Bus with

Interrupt

The PCA9535E and PCA9535EC devices provide 16 bits of

General Purpose parallel Input / Output (GPIO) expansion through the

I C−bus / SMBus.

http://onsemi.com

MARKING

The PCA9535E and PCA9535EC consist of two 8−bit

Configuration (Input or Output selection); Input, Output and Polarity

Inversion (active−HIGH or active−LOW operation) registers. At

power on, all I/Os default to inputs. Each I/O may be configured as

either input or output by writing to its corresponding I/O configuration

bit. The data for each Input or Output is kept in its corresponding Input

or Output register. The Polarity Inversion register may be used to

invert the polarity if the read register. All registers can be read by the

system master.

DIAGRAMS

PCA9535E(C)

AWLYYWWG

SOIC−24

DW SUFFIX

CASE 751E

The PCA9535E, identical to the PCA9655E but with the internal

I/O pull−up resistors removed, has greatly reduced power

consumption when the I/Os are held LOW.

PCA95

35E(C)

AWLYYWWG

The PCA9535EC is identical to the PCA9535E but with

high−impedance open−drain outputs at all the I/O pins.

TSSOP−24

DT SUFFIX

CASE 948H

The PCA9535E and PCA9535EC provide an open−drain interrupt

output which is activated when any input state differs from its

corresponding input port register state. The interrupt output is used to

indicate to the system master that an input state has changed. The

power−on reset sets the registers to their default values and initializes

the device state machine.

PCA

9535E(C)

ALYWG

WQFN24

MT SUFFIX

CASE 485BG

Three hardware pins (AD0, AD1, AD2) are used to configure the

I C−bus slave address of the device. The I C−bus slave addresses of

the PCA9535E and PCA9535EC are the same as the PCA9655E. This

allows up to 64 of these devices in any combination to share the same

XXXX = Specific Device Code

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

I C−bus/SMBus.

Features

G or G = Pb−Free Package

• V Operating Range: 1.65 V to 5.5 V

(Note: Microdot may be in either location)

• SDA Sink Capability: 30 mA

• 5.5 V Tolerant I/Os

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

• Polarity Inversion Register

• Active LOW Interrupt Output

• Low Standby Current

• Noise Filter on SCL/SDA Inputs

• No Glitch on Power−up

• Internal Power−on Reset

• 64 Programmable Slave Addresses using Three

Address Pins

• I C SCL Clock Frequencies Supported:

Standard Mode: 100 kHz

Fast Mode: 400 kHz

Fast Mode +: 1 MHz

• ESD Performance: 3000 V Human Body Model, 400 V

Machine Model

• 16 I/O Pins which Default to 16 Inputs

• These are Pb−Free Devices

Semiconductor Components Industries, LLC, 2012

Publication Order Number:

August, 2012 − Rev. 2

PCA9535E/D

12 3 4 5 6 7...20

中文翻译

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