Datasheet > NLVU1GT125AMUTCG

NLVU1GT125AMUTCG

更新时间： 2024-11-21 11:11:31

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
6页	193K
描述
Single Non-Inverting Buffer, 3-State

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NLVU1GT125AMUTCG 数据手册

NLU1GT125

Non-Inverting 3-State

Buffer, TTL Level

LSTTL−Compatible Inputs

The NLU1GT125 MiniGatet is an advanced CMOS high−speed

non−inverting buffer in ultra−small footprint.

The NLU1GT125 requires the 3−state control input OE to be set

High to place the output in the high impedance state.

The device input is compatible with TTL−type input thresholds and

the output has a full 5.0 V CMOS level output swing.

www.onsemi.com

MARKING

DIAGRAMS

The NLU1GT125 input and output structures provide protection

when voltages up to 7.0 V are applied, regardless of the supply voltage.

UDFN6

1.2 x 1.0

CASE 517AA

Features

• High Speed: t = 3.8 ns (Typ) @ V = 5.0 V

• Low Power Dissipation: I = 1 mA (Max) at T = 25°C

UDFN6

1.0 x 1.0

CASE 517BX

• TTL−Compatible Input: V = 0.8 V; V = 2.0 V

L M

• CMOS−Compatible Output:

> 0.8 V ; V < 0.1 V @ Load

CC OL CC

• Power Down Protection Provided on inputs

• Balanced Propagation Delays

• Ultra−Small Packages

UDFN6

1.45 x 1.0

CASE 517AQ

D M

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These are Pb−Free Devices

= Device Marking

= Date Code

ORDERING INFORMATION

See detailed ordering and shipping information on page 4 of

this data sheet.

IN A

GND

OUT Y

Figure 1. Pinout (Top View)

IN A

OUT Y

Figure 2. Logic Symbol

FUNCTION TABLE

PIN ASSIGNMENT

IN A

Input

Output

GND

OUT Y

Publication Order Number:

January, 2019 − Rev. 7

NLU1GT125/D

12 3 4 5 6

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