Datasheet > NLV74HC74ADTR2G

NLV74HC74ADTR2G

更新时间： 2024-11-10 01:13:11

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
7页	116K
描述
Dual D Flip-Flop with Set and Reset

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NLV74HC74ADTR2G 数据手册

MC74HC74A

Dual D Flip-Flop with Set

and Reset

High−Performance Silicon−Gate CMOS

The MC74HC74A is identical in pinout to the LS74. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

http://onsemi.com

This device consists of two D flip−flops with individual Set, Reset,

and Clock inputs. Information at a D−input is transferred to the

corresponding Q output on the next positive going edge of the clock

input. Both Q and Q outputs are available from each flip−flop. The Set

and Reset inputs are asynchronous.

SOIC−14 NB

D SUFFIX

CASE 751A

TSSOP−14

DT SUFFIX

CASE 948G

PIN ASSIGNMENT

Features

RESET 1

DATA 1

13 RESET 2

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

CLOCK 1

SET 1

DATA 2

• Low Input Current: 1.0 mA

11 CLOCK 2

10 SET 2

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 128 FETs or 32 Equivalent Gates

GND

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

MARKING DIAGRAMS

• These Devices are Pb−Free, Halogen Free and are RoHS Compliant

HC74AG

AWLYWW

LOGIC DIAGRAM

RESET 1

SOIC−14 NB

DATA 1

CLOCK 1

74A

ALYWG

SET 1

RESET 2

TSSOP−14

DATA 2

L, WL

Y, YY

= Assembly Location

= Wafer Lot

= Year

CLOCK 2

SET 2

W, WW = Work Week

PIN 14 = V

PIN 7 = GND

G or G

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

Publication Order Number:

August, 2014 − Rev. 14

MC74HC74A/D

12 3 4 5 6 7

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