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NLV74HCT74ADG

更新时间: 2024-11-26 11:01:43
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器
页数 文件大小 规格书
6页 135K
描述
双 D 型触发器,带设置和重置

NLV74HCT74ADG 数据手册

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MC74HCT74A  
Dual D Flip−Flop with Set  
and Reset with LSTTL  
Compatible Inputs  
HighPerformance SiliconGate CMOS  
The MC74HCT74A is identical in pinout to the LS74. This device  
may be used as a level converter for interfacing TTL or NMOS outputs  
to High Speed CMOS inputs.  
http://onsemi.com  
MARKING  
DIAGRAMS  
This device consists of two D flipflops with individual Set, Reset,  
and Clock inputs. Information at a Dinput is transferred to the  
corresponding Q output on the next positive going edge of the clock  
input. Both Q and Q outputs are available from each flipflop. The Set  
and Reset inputs are asynchronous.  
14  
PDIP14  
N SUFFIX  
CASE 646  
MC74HCT74AN  
AWLYYWWG  
14  
1
1
Features  
14  
Output Drive Capability: 10 LSTTL Loads  
TTL NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 mA  
In Compliance With the JEDEC Standard No. 7.0 A Requirements  
Chip Complexity: 136 FETs or 34 Equivalent Gates  
PbFree Packages are Available  
SOIC14  
D SUFFIX  
CASE 751A  
HCT74AG  
AWLYWW  
14  
1
1
A
= Assembly Location  
L, WL = Wafer Lot  
Y, YY = Year  
W, WW = Work Week  
= PbFree Package  
G
PIN ASSIGNMENT  
LOGIC DIAGRAM  
RESET 1  
DATA 1  
1
2
14  
13 RESET 2  
12  
V
CC  
1
RESET 1  
3
4
CLOCK 1  
SET 1  
DATA 2  
5
6
2
3
DATA 1  
Q1  
Q1  
11 CLOCK 2  
10 SET 2  
Q1  
Q1  
5
6
7
CLOCK 1  
9
8
Q2  
Q2  
4
SET 1  
GND  
PIN 14 = V  
CC  
PIN 7 = GND  
13  
RESET 2  
FUNCTION TABLE  
9
12  
11  
Inputs  
Outputs  
DATA 2  
Q2  
8
Set Reset Clock Data  
Q
Q
CLOCK 2  
Q2  
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*  
H
L
L
H
H*  
L
10  
SET 2  
Design Criteria  
Internal Gate Count†  
Value  
34  
Units  
ea.  
ns  
H
L
H
No Change  
No Change  
No Change  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
1.5  
5.0  
mW  
pJ  
*Both outputs will remain high as long as Set and  
Reset are low, but the output states are unpredict-  
able if Set and Reset go high simultaneously.  
.0075  
†Equivalent to a twoinput NAND gate.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
October, 2006 Rev. 10  
MC74HCT74A/D  

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