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NLHV4052DTR2G PDF预览

NLHV4052DTR2G

更新时间: 2024-09-14 02:49:15
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安森美 - ONSEMI /
页数 文件大小 规格书
11页 128K
描述
Analog Multiplexers/Demultiplexers

NLHV4052DTR2G 数据手册

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NLHV4051, NLHV4052,  
NLHV4053  
Analog  
Multiplexers/Demultiplexers  
The NLHV4051, NLHV4052, and NLHV4053 analog multiplexers  
are digitally−controlled analog switches. The NLHV4051 effectively  
implements an SP8T solid state switch, the NLHV4052 a DP4T, and  
the NLHV4053 a Triple SPDT. All three devices feature low ON  
impedance and very low OFF leakage current. Control of analog  
signals up to the complete supply voltage range can be achieved.  
www.onsemi.com  
Features  
1
1
SOIC−16  
D SUFFIX  
CASE 751B  
TSSOP−16  
DT SUFFIX  
CASE 948F  
Triple Diode Protection on Control Inputs  
Switch Function is Break Before Make  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Analog Voltage Range (V − V ) = 3.0 to 18 V  
DD  
EE  
MARKING DIAGRAMS  
Note: V must be V  
EE  
SS  
16  
Linearized Transfer Characteristics  
NLHVG  
405x  
AWLYWW  
Low−noise − 12 nV/Cycle, f 1.0 kHz Typical  
Pin−for−Pin Replacement for CD4051, CD4052, and CD4053  
For 4PDT Switch, See MC14551B  
1
SOIC−16  
For Lower R , Use the HC4051, HC4052, or HC4053 High−Speed  
ON  
CMOS Devices  
16  
1
These Devices are Pb−Free and are RoHS Compliant  
NLHV  
405x  
ALYWG  
G
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
Unit  
V
DD  
DC Supply Voltage Range  
−0.5 to +18.0  
V
TSSOP−16  
(Referenced to V , V V )  
EE  
SS  
EE  
V ,  
Input or Output Voltage Range  
(DC or Transient) (Referenced to V for  
−0.5 to V + 0.5  
V
in  
DD  
x
A
WL, L  
Y
= 1, 2, or 3  
= Assembly Location  
= Wafer Lot  
V
out  
SS  
Control Inputs and V for Switch I/O)  
EE  
I
in  
Input Current (DC or Transient)  
per Control Pin  
+10  
mA  
= Year  
WW, W = Work Week  
G or G  
= Pb−Free Package  
I
Switch Through Current  
25  
500  
mA  
mW  
°C  
SW  
(Note: Microdot may be in either location)  
P
Power Dissipation per Package (Note 1)  
Ambient Temperature Range  
D
T
−55 to +125  
−65 to +150  
260  
A
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
T
Storage Temperature Range  
°C  
stg  
T
Lead Temperature (8−Second Soldering)  
°C  
L
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained to  
in  
out  
the range V (V or V ) V .  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either  
V
, V or V ). Unused outputs must be left open.  
SS EE  
DD  
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
April, 2017 − Rev. 0  
NLHV4051/D  
 

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