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NL74VCX16374DTR2

更新时间： 2024-02-25 20:13:26
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 317K
描述
16-Bit D-Type Flip-Flop

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中文翻译

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NL74VCX16374DTR2 技术参数

是否Rohs认证： 不符合生命周期：Active
Reach Compliance Code：unknown风险等级：5.83
Is Samacsys：NJESD-30 代码：R-PDSO-G48
JESD-609代码：e0负载电容（CL）：30 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：250000000 Hz
最大I（ol）：0.024 A功能数量：16
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
电源：3.3 VProp。Delay @ Nom-Sup：3 ns
认证状态：Not Qualified子类别：FF/Latches
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
触发器类型：POSITIVE EDGEBase Number Matches：1

NL74VCX16374DTR2 数据手册

 浏览型号NL74VCX16374DTR2的Datasheet PDF文件第2页浏览型号NL74VCX16374DTR2的Datasheet PDF文件第3页浏览型号NL74VCX16374DTR2的Datasheet PDF文件第4页浏览型号NL74VCX16374DTR2的Datasheet PDF文件第5页浏览型号NL74VCX16374DTR2的Datasheet PDF文件第6页浏览型号NL74VCX16374DTR2的Datasheet PDF文件第7页 
With 3.6V–Tolerant Inputs and Outputs  
(3–State, Non–Inverting)  
The NL74VCX16374 is an advanced performance, non–inverting  
16–bit D–type flip–flop. It is designed for very high–speed, very  
low–power operation in 1.8V, 2.5V or 3.3V systems. The VCX16374  
is byte controlled, with each byte functioning identically, but  
independently. Each byte has separate Output Enable and Clock Pulse  
inputs. These control pins can be tied together for full 16–bit  
operation.  
When operating at 2.5V (or 1.8V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3V busses. It is guaranteed to be over–voltage tolerant to 3.6V.  
The NL74VCX16374 consists of 16 edge–triggered flip–flops with  
individual D–type inputs and 3.6V–tolerant 3–state outputs. The  
clocks (CPn) and Output Enables (OEn) are common to all flip–flops  
within the respective byte. The flip–flops will store the state of  
individual D inputs that meet the setup and hold time requirements on  
the LOW–to–HIGH Clock (CP) transition. With the OE LOW, the  
contents of the flip–flops are available at the outputs. When the OE is  
HIGH, the outputs go to the high impedance state. The OE input level  
does not affect the operation of the flip–flops.  
http://onsemi.com  
48  
1
TSSOP–48  
DT SUFFIX  
CASE 1201  
MARKING DIAGRAM  
48  
NL74VCX16374DT  
AWLYYWW  
1
• Designed for Low Voltage Operation: V  
• 3.6V Tolerant Inputs and Outputs  
= 1.65–3.6V  
A
= Assembly Location  
CC  
WL = Wafer Lot  
YY = Year  
• High Speed Operation: 3.0ns max for 3.0 to 3.6V  
3.9ns max for 2.3 to 2.7V  
WW = Work Week  
7.8ns max for 1.65 to 1.95V  
• Static Drive: ±24mA Drive at 3.0V  
±18mA Drive at 2.3V  
PIN NAMES  
Pins  
Function  
±6mA Drive at 1.65V  
OEn  
CPn  
D0–D15  
O0–O15  
Output Enable Inputs  
Clock Pulse Inputs  
Inputs  
• Supports Live Insertion and Withdrawal  
• I  
Specification Guarantees High Impedance When V = 0V  
OFF  
CC  
Outputs  
• Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds ±300mA @ 125°C  
• ESD Performance: Human Body Model >2000V; Machine Model  
ORDERING INFORMATION  
>200V  
Device  
Package  
TSSOP  
TSSOP  
Shipping  
39 / Rail  
NL74VCX16374DT  
NL74VCX16374DTR2  
2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 0  
NL74VCX16374/D  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
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