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NL74VCXH16240DTR PDF预览

NL74VCXH16240DTR

更新时间: 2024-01-16 07:28:17
品牌 Logo 应用领域
其他 - ETC 驱动器
页数 文件大小 规格书
12页 310K
描述
Quad 4-Bit Buffer/Driver

NL74VCXH16240DTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:not_compliant
风险等级:5.3控制类型:ENABLE LOW
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
负载电容(CL):30 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.018 A位数:4
功能数量:4端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:2.5 ns
传播延迟(tpd):6 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

NL74VCXH16240DTR 数据手册

 浏览型号NL74VCXH16240DTR的Datasheet PDF文件第2页浏览型号NL74VCXH16240DTR的Datasheet PDF文件第3页浏览型号NL74VCXH16240DTR的Datasheet PDF文件第4页浏览型号NL74VCXH16240DTR的Datasheet PDF文件第5页浏览型号NL74VCXH16240DTR的Datasheet PDF文件第6页浏览型号NL74VCXH16240DTR的Datasheet PDF文件第7页 
With 3.6V–Tolerant Inputs and Outputs  
(3–State, Inverting)  
The NL74VCXH16240 is an advanced performance, inverting  
16–bit buffer. It is designed for very high–speed, very low–power  
operation in 1.8V, 2.5V or 3.3V systems.  
http://onsemi.com  
When operating at 2.5V (or 1.8V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3V busses. It is guaranteed to be over–voltage tolerant to 3.6V.  
The NL74VCXH16240 is nibble controlled with each nibble  
functioning identically, but independently. The control pins may be  
tied together to obtain full 16–bit operation. The 3–state outputs are  
controlled by an Output Enable (OEn) input for each nibble. When  
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are  
in the high impedance state. The data inputs include active bushold  
circuitry, eliminating the need for external pull–up resistors to hold  
unused or floating inputs at a valid logic state.  
48  
1
TSSOP–48  
DT SUFFIX  
CASE 1201  
MARKING DIAGRAM  
48  
NL74VCXH16240DT  
AWLYYWW  
Designed for Low Voltage Operation: V  
3.6V Tolerant Inputs and Outputs  
= 1.65–3.6V  
CC  
High Speed Operation: 2.5ns max for 3.0 to 3.6V  
3.0ns max for 2.3 to 2.7V  
6.0ns max for 1.65 to 1.95V  
Static Drive: ±24mA Drive at 3.0V  
±18mA Drive at 2.3V  
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
±6mA Drive at 1.65V  
Supports Live Insertion and Withdrawal  
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid  
PIN NAMES  
Logic State  
Pins  
Function  
I  
Specification Guarantees High Impedance When V = 0V†  
CC  
OFF  
Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
OEn  
D0–D15  
O0–O15  
Output Enable Inputs  
Inputs  
Outputs  
Latchup Performance Exceeds ±300mA @ 125°C  
ESD Performance: Human Body Model >2000V; Machine Model  
>200V  
†NOTE: To ensure the outputs activate in the 3–state condition, the output  
enable pins should be connected to V  
value of the resistor is determined by the current sinking capability of the  
output connected to the OE pin.  
through a pull–up resistor. The  
CC  
ORDERING INFORMATION  
Device  
Package  
TSSOP  
TSSOP  
Shipping  
39 / Rail  
NL74VCXH16240DT  
NL74VCXH16240DTR  
2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 0  
NL74VCXH16240/D  
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