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NL74VCXH16245DT PDF预览

NL74VCXH16245DT

更新时间： 2024-01-09 19:17:14
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其他 - ETC 总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 313K
描述
Dual 8-bit Bus Transceiver

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NL74VCXH16245DT 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP-48
针数：48Reach Compliance Code：not_compliant
风险等级：5.33Is Samacsys：N
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：12.5 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.024 A位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：2.5 ns
传播延迟（tpd）：6 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：6.1 mmBase Number Matches：1

NL74VCXH16245DT 数据手册

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With 3.6V–Tolerant Inputs and Outputs  
(3–State, Non–Inverting)  
The NL74VCXH16245 is an advanced performance, non–inverting  
16–bit transceiver. It is designed for very high–speed, very low–power  
operation in 1.8V, 2.5V or 3.3V systems.  
http://onsemi.com  
When operating at 2.5V (or 1.8V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3V busses. It is guaranteed to be over–voltage tolerant to 3.6V.  
The VCXH16245 is designed with byte control. It can be operated  
as two separate octals, or with the controls tied together, as a 16–bit  
wide function. The Transmit/Receive (T/Rn) inputs determine the  
direction of data flow through the bi–directional transceiver. Transmit  
(active–HIGH) enables data from A ports to B ports; Receive  
(active–LOW) enables data from B to A ports. The Output Enable  
inputs (OEn), when HIGH, disable both A and B ports by placing them  
in a HIGH Z condition. The data inputs include active bushold  
circuitry, eliminating the need for external pull–up resistors to hold  
unused or floating inputs at a valid logic state.  
48  
1
TSSOP–48  
DT SUFFIX  
CASE 1201  
MARKING DIAGRAM  
48  
NL74VCXH16245DT  
AWLYYWW  
• Designed for Low Voltage Operation: V  
• 3.6V Tolerant Inputs and Outputs  
• High Speed Operation: 2.5ns max for 3.0 to 3.6V  
3.0ns max for 2.3 to 2.7V  
= 1.65–3.6V  
CC  
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
6.0ns max for 1.65 to 1.95V  
WW = Work Week  
• Static Drive: ±24mA Drive at 3.0V  
±18mA Drive at 2.3V  
±6mA Drive at 1.65V  
PIN NAMES  
• Supports Live Insertion and Withdrawal  
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid  
Pins  
Function  
Logic State  
OEn  
Output Enable Inputs  
†
T/Rn  
A0–A15  
B0–B15  
Transmit/Receive Inputs  
Side A Inputs or 3–State Outputs  
Side B Inputs or 3–State Outputs  
• I  
Specification Guarantees High Impedance When V = 0V  
CC  
OFF  
• Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds ±300mA @ 125°C  
• ESD Performance: Human Body Model >2000V; Machine Model  
ORDERING INFORMATION  
>200V  
†NOTE: To ensure the outputs activate in the 3–state condition, the output  
Device  
Package  
TSSOP  
TSSOP  
Shipping  
39 / Rail  
enable pins should be connected to V  
through a pull–up resistor. The  
CC  
NL74VCXH16245DT  
NL74VCXH16245DTR  
value of the resistor is determined by the current sinking capability of the  
output connected to the OE pin.  
2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 0  
NL74VCXH16245/D  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
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