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NL7SZ18DFT2 PDF预览

NL7SZ18DFT2

更新时间: 2024-01-27 19:04:05
品牌 Logo 应用领域
安森美 - ONSEMI 解码器驱动器解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 71K
描述
1−of−2 Non−Inverting Demultiplexer with 3−State Deselected Output

NL7SZ18DFT2 技术参数

是否无铅:含铅生命周期:Active
零件包装代码:SOT-363包装说明:LEAD FREE, SC-70, SC-88, SOT-363, 6 PIN
针数:6Reach Compliance Code:unknown
风险等级:5.7Is Samacsys:N
系列:LVC/LCX/Z输入调节:STANDARD
JESD-30 代码:R-PDSO-G6JESD-609代码:e3
长度:2 mm逻辑集成电路类型:OTHER DECODER/DRIVER
湿度敏感等级:NOT SPECIFIED功能数量:1
端子数量:6最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):10.5 ns认证状态:COMMERCIAL
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:1.25 mmBase Number Matches:1

NL7SZ18DFT2 数据手册

 浏览型号NL7SZ18DFT2的Datasheet PDF文件第2页浏览型号NL7SZ18DFT2的Datasheet PDF文件第3页浏览型号NL7SZ18DFT2的Datasheet PDF文件第4页浏览型号NL7SZ18DFT2的Datasheet PDF文件第5页浏览型号NL7SZ18DFT2的Datasheet PDF文件第6页浏览型号NL7SZ18DFT2的Datasheet PDF文件第7页 
NL7SZ18  
1−of−2 Non−Inverting  
Demultiplexer with 3−State  
Deselected Output  
The NL7SZ18 is a high−performance 1−to−2 Demultiplexer  
operating from a 1.65 V to 5.5 V supply. When the select pin [S] is  
enabled [high or low], the data in the address pin [A] is routed to one of  
http://onsemi.com  
MARKING DIAGRAMS  
the output pins [Y or Y ], maintaining a high−impedance on the  
0
1
deselected output pin (See Truth Table).  
This device has been optimized for on−board buffering applications  
and offers mixed (1.65 V, 2.3 V, 3.0 V and 5.5 V) voltage capability by  
providing over voltage tolerance (OVT*) circuitry on I/O pins.  
LD M G  
1
G
SOT−363/SC70−6/SC−88  
DF SUFFIX  
1
CASE 419B  
Features  
High−Speed Propagation Delay  
t
2.5 nS (Typ), Load 50 pF @ 5.0 V  
PD  
T M  
G
Power Down Impedance  
Outputs in High−Z  
1
Output Drive Capability  
32 mA @ 5.0 V  
UDFN6  
MU SUFFIX  
CASE 517AA  
Broad V Operating Range  
CC  
1.65 V to 5.5 V  
LD, T  
= Device Marking  
= Date Code*  
= Pb−Free Package  
M
G
Surface Mount Technology  
SC−70, 6−Lead Packaging  
OVT* on Inputs/Outputs  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
Pb−Free Package is Available  
PIN ASSIGNMENT  
Typical Applications  
Cell Phones  
PDAs  
1
6
S
Y
0
Digital Cameras  
Video Cameras  
2
3
5
4
GND  
A
V
Y
CC  
1
Important Information  
ESD Protection: MM >200 V, Human Body Model >2000 V  
Latch−Up Max Rating: 300 mA  
Pin−to−Pin Compatible with NC7SZ18  
(TOP VIEW)  
*Over Voltage Tolerance (OVT) enables input and output pins to function outside  
(higher) of their operating voltages, with no damage to the devices or to signal  
integrity.  
TRUTH TABLE  
Input  
Output  
PIN/FUNCTION TABLE  
S
A
Y
Y
1
0
L
L
H
H
L
H
L
L
Z
Z
L
Pin  
Function  
H
Z
Z
A
Data Input  
H
H
S
Demultiplexer Select  
Output 1  
Y
Y
0
1
Output 2  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 6  
NL7SZ18/D  

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