Datasheet > NL17SHT00

NL17SHT00

更新时间： 2024-02-20 18:42:24

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
5页	103K
描述
Single 2-Input NAND Gate CMOS Logic Level Shifter

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NL17SHT00 数据手册

NL17SHT00

Single 2-Input NAND Gate/

CMOS Logic Level Shifter

LSTTL−Compatible Inputs

The NL17SHT00 is a single gate 2−input NAND fabricated with

silicon gate CMOS technology.

http://onsemi.com

MARKING

The internal circuit is composed of multiple stages, including a

buffer output which provides high noise immunity and stable output.

The device input is compatible with TTL−type input thresholds and

the output has a full 5 V CMOS level output swing. The input

protection circuitry on this device allows overvoltage tolerance on the

input, allowing the device to be used as a logic−level translator from

3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to

3 V CMOS Logic while operating at the high voltage power supply.

The NL17SHT00 input structure provides protection when voltages

up to 7 V are applied, regardless of the supply voltage. This allows the

NL17SHT00 to be used to interface 5 V circuits to 3 V circuits. The

DIAGRAM

SOT−953

CASE 527AE

= Specific Device Code

= Month Code

output structures also provide protection when V = 0 V. These

PIN ASSIGNMENT

input and output structures help prevent device destruction caused by

supply voltage − input/output voltage mismatch, battery backup, hot

insertion, etc.

IN A

GND

IN B

Features

OUT Y

• High Speed: t = 3.1 ns (Typ) at V = 5 V

• Low Power Dissipation: I = 1 mA (Max) at T = 25°C

• TTL−Compatible Inputs: V = 0.8 V; V = 2 V

FUNCTION TABLE

• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load

Inputs

Output

• Power Down Protection Provided on Inputs and Outputs

• Balanced Propagation Delays

• Pin and Function Compatible with Other Standard Logic Families

• These are Pb−Free Devices

IN A

GND

IN B

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

OUT Y

Figure 1. Pinout

IN A

IN B

OUT Y

Figure 2. Logic Symbol

Publication Order Number:

August, 2011 − Rev. 0

NL17SHT00/D

12 3 4 5

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