Datasheet > NL17SHT126

NL17SHT126

更新时间： 2024-01-17 18:24:32

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
5页	108K
描述
Noninverting Buffer CMOS Logic Level Shifter

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NL17SHT126 数据手册

NL17SHT126

Noninverting Buffer /

CMOS Logic Level Shifter

with LSTTL−Compatible Inputs

The NL17SHT126 is a single gate noninverting 3−state buffer

fabricated with silicon gate CMOS technology. It achieves high speed

operation similar to equivalent Bipolar Schottky TTL while maintaining

CMOS low power dissipation.

The NL17SHT126 requires the 3−state control input (OE) to be set

Low to place the output into the high impedance state.

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MARKING

DIAGRAM

The device input is compatible with TTL−type input thresholds and

the output has a full 5 V CMOS level output swing. The input

protection circuitry on this device allows overvoltage tolerance on the

input, allowing the device to be used as a logic−level translator from

3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to

3 V CMOS Logic while operating at the high−voltage power supply.

The NL17SHT126 input structure provides protection when

voltages up to 7 V are applied, regardless of the supply voltage. This

allows the NL17SHT126 to be used to interface 5 V circuits to 3 V

circuits. The output structures also provide protection when

SOT−953

CASE 527AE

= Specific Device Code

= Month Code

PIN ASSIGNMENT

IN A

GND

= 0 V. These input and output structures help prevent device

destruction caused by supply voltage − input/output voltage mismatch,

battery backup, hot insertion, etc.

OUT Y

Features

• High Speed: t = 3.5 ns (Typ) at V = 5 V

• Low Power Dissipation: I = 1 mA (Max) at T = 25°C

FUNCTION TABLE

OE Input

• TTL−Compatible Inputs: V = 0.8 V; V = 2 V

A Input

Y Output

• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load

• Power Down Protection Provided on Inputs and Outputs

• Balanced Propagation Delays

• Pin and Function Compatible with Other Standard Logic Families

• These are Pb−Free Devices

ORDERING INFORMATION

IN A

GND

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

OUT Y

Figure 1. Pinout (Top View)

IN A

OUT Y

Figure 2. Logic Symbol

Publication Order Number:

August, 2011 − Rev. 0

NL17SHT126/D

12 3 4 5

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